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Intel(R) Advanced Boot Block Flash Memory (B3)
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet
Product Features
* Flexible SmartVoltage Technology
-- 2.7 V - 3.6 V read/program/erase -- 12 V V PP fast production programming
* Intel(R) Flash Data Integrator Software
--Flash Memory Manager --System Interrupt Manager --Supports parameter storage, streaming data (for example, voice)
* 1.65 V - .5 V or 2.7 V - 3.6 V I/O option
-- Reduces overall system power
* High Performance
-- 2.7 V - 3.6 V: 70 ns max access time
* Extended Cycling Capability
--Minimum 100,000 block erase cycles
* Optimized Block Sizes
-- Eight 8-KB blocks for data, top or bottom locations -- Up to 127 x 64-KB blocks for code
* Automatic Power Savings Feature
--Typical ICCS after bus inactivity
* Standard Surface Mount Packaging
--48-Ball CSP packages --40-Lead and 48-Lead TSOP packages
* Block Locking
-- VCC-level control through Write Protect WP#
* Density and Footprint Upgradeable for
common package --8-, 16-, 32-, and 64-Mbit densities
* Low Power Consumption
-- 9 mA typical read current
* ETOXTM VIII (0.13 m) Flash
Technology --16-Mbit and 32-Mbit densities
* Absolute Hardware-Protection
-- VPP = GND option -- VCC lockout voltage
* ETOXTM VII (0.18 m) Flash Technology
--16-, 32-, and 64-Mbit densities
* Extended Temperature Operation
-- -40 C to +85 C
* ETOX TM VI (0.25m) Flash Technology
--8-, 16-, and 32-Mbit densities
* Automated Program and Block Erase
-- Status registers
* Bo not use the x8 option for new designs
The Intel(R) Advanced Boot Block Flash Memory (B3) device, manufactured on the Intel 0.13 m and 0.18 m technologies, is a feature-rich solution at a low system cost. The B3 device in x16 is available in 48-lead TSOP and 48-ball CSP packages. The x8 option of this product family is available only in 40-lead TSOP and 48-ball BGA* packages. For additional information about this product family, see the Intel website: http://www.intel.com/design/flash.
Notice: This specification is subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Order Number: 290580, Revision: 020 18 Aug 2005
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. The Intel(R) Advanced Boot Block Flash Memory (B3) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800 548-4725 or by visiting Intel's website at http://www.intel.com. Intel, the Intel logo, and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 2005, Intel Corporation.
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Datasheet
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Contents
1.0 Introduction ............................................................................................................................... 7
1.1 1.2 Nomenclature ....................................................................................................................... 7 Conventions .......................................................................................................................... 8
2.0 Functional Overview .............................................................................................................. 8 3.0 Functional Overview .............................................................................................................. 9
3.1 3.2 Architecture Diagram .......................................................................................................... 10 Memory Maps and Block Organization ............................................................................... 11 3.2.1 Parameter Blocks .................................................................................................. 11 3.2.2 Main Blocks ........................................................................................................... 11 3.2.3 4-Mbit, 8-Mbit, 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Maps ............. 11 3.2.4 4-Mbit, 8-Mbit, and 16-Mbit Byte-Wide Memory Maps........................................... 20
4.0 Package Information ............................................................................................................ 24
4.1 4.2 4.3 mBGA* and Very Thin Profile Fine Pitch Ball Grid Array (VF BGA) Package .................... 24 TSOP Package ................................................................................................................... 25 Easy BGA Package ............................................................................................................ 26
5.0 Pinout and Signal Descriptions.......................................................................................27
5.1 5.2 Signal Pinouts ..................................................................................................................... 27 5.1.1 40-Lead and 48-Lead TSOP Packages ................................................................. 27 Signal Descriptions ............................................................................................................. 30
6.0 Maximum Ratings and Operating Conditions ...........................................................32
6.1 6.2 Absolute Maximum Ratings ................................................................................................ 32 Operating Conditions .......................................................................................................... 33
7.0 Electrical Specifications ..................................................................................................... 34
7.1 7.2 DC Current Characteristics .................................................................................................34 DC Voltage Characteristics.................................................................................................36
8.0 AC Characteristics ................................................................................................................ 37
8.1 8.2 8.3 8.4 8.5 AC Read Characteristics .................................................................................................... 37 AC Write Characteristics..................................................................................................... 41 Erase and Program Timing .................................................................................................45 AC I/O Test Conditions ....................................................................................................... 46 Device Capacitance ............................................................................................................ 46
9.0 Power and Reset Specifications .....................................................................................47
9.1 Power-Up/Down Characteristics ......................................................................................... 47 9.1.1 RP# Connected to System Reset .......................................................................... 47 9.1.2 VCC, VPP, and RP# Transitions..............................................................................47 Reset Specifications ........................................................................................................... 48 Power Supply Decoupling................................................................................................... 49
9.2 9.3
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9.4
Power Consumption ........................................................................................................... 49 9.4.1 Active Power.......................................................................................................... 49 9.4.2 Automatic Power Savings (APS) ........................................................................... 49 9.4.3 Standby Power ...................................................................................................... 49 9.4.4 Deep Power-Down Mode....................................................................................... 50
10.0 Operations Overview ........................................................................................................... 50
10.1 Bus Operations ................................................................................................................... 51 10.1.1 Read ...................................................................................................................... 51 10.1.2 Output Disable ....................................................................................................... 52 10.1.3 Standby.................................................................................................................. 52 10.1.4 Deep Power-Down / Reset .................................................................................... 52 10.1.5 Write ...................................................................................................................... 53
11.0 Operating Modes ................................................................................................................... 53
11.1 11.2 11.3 11.4 11.5 Read Array.......................................................................................................................... 54 Read Identifier .................................................................................................................... 56 Read Status Register.......................................................................................................... 56 11.3.1 Clearing the Status Register.................................................................................. 57 Program Mode .................................................................................................................... 57 11.4.1 Suspending and Resuming Programming ............................................................. 58 Erase Mode ........................................................................................................................ 58 11.5.1 Suspending and Resuming Erase ......................................................................... 59
12.0 Block Locking ......................................................................................................................... 62
12.1 12.2 WP# = VIL for Block Locking............................................................................................... 62 WP# = VIH for Block Unlocking........................................................................................... 62 VPP = VIL for Complete Protection...................................................................................... 63
13.0 VPP Program and Erase Voltages ................................................................................... 63
13.1
14.0 Additional Information ........................................................................................................ 63 Appendix A Appendix B Appendix C Write State Machine Current/Next States ................................................. 64 Program and Erase Flowcharts .................................................................... 66 Ordering Information.........................................................................................70
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Revision History
Revision Number -001 Original version Section 3.4, VPP Program and Erase Voltages, added Updated Figure 9: Automated Block Erase Flowchart Updated Figure 10: Erase Suspend/Resume Flowchart (added program to table) Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes) IPPR maximum specification change from 25 A to 50 A Program and Erase Suspend Latency specification change Updated Appendix A: Ordering Information (included 8 M and 4 M information) Updated Figure, Appendix D: Architecture Block Diagram (Block info. in words not bytes) Minor wording changes Combined byte-wide specification (previously 290605) with this document Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V) Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4) Improved several DC characteristics (Section 4.4) Improved several AC characteristics (Sections 4.5 and 4.6) Combined 2.7 V and 1.8 V DC characteristics (Section 4.4) Added 5 V VPP read specification (Section 3.4) Removed 120 ns and 150 ns speed offerings Moved Ordering Information from Appendix to Section 6.0; updated information Moved Additional Information from Appendix to Section 7.0 Updated figure Appendix B, Access Time vs. Capacitive Load Updated figure Appendix C, Architecture Block Diagram Moved Program and Erase Flowcharts to Appendix E Updated Program Flowchart Updated Program Suspend/Resume Flowchart Minor text edits throughout Added 32-Mbit density Added 98H as a reserved command (Table 4) A 1-A20 = 0 when in read identifier mode (Section 3.2.2) Status register clarification for SR3 (Table 7) VCC and VCCQ absolute maximum specification = 3.7 V (Section 4.1) Combined IPPW and ICCW into one specification (Section 4.4) Combined IPPE and ICCE into one specification (Section 4.4) Max Parameter Block Erase Time (tWHQV2/tEHQV2) reduced to 4 sec (Section 4.7) Max Main Block Erase Time (tWHQV3/tEHQV3) reduced to 5 sec (Section 4.7) Erase suspend time @ 12 V (tWHRH2/tEHRH2) changed to 5 s typical and 20 s maximum (Section 4.7) Ordering Information updated (Section 6.0) Write State Machine Current/Next States Table updated (Appendix A) Program Suspend/Resume Flowchart updated (Appendix F) Erase Suspend/Resume Flowchart updated (Appendix F) Text clarifications throughout BGA package diagrams corrected (Figures 3 and 4) IPPD test conditions corrected (Section 4.4) 32-Mbit ordering information corrected (Section 6) BGA package top side mark information added (Section 6) VIH and VILSpecification change (Section 4.4) ICCS test conditions clarification (Section 4.4) Added Command Sequence Error Note (Table 7) Data sheet renamed from Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash Memory Family. Added device ID information for 4-Mbit x8 device Removed 32-Mbit x8 to reflect product offerings Minor text changes Description
-002
-003
-004
-005
-006
Datasheet
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Revision Number -007 -008 -009 -010 -011
Description Corrected RP# pin description in Table 2, 3 Volt Advanced Boot Block Pin Descriptions Corrected typographical error fixed in Ordering Information 4-Mbit packaging and addressing information corrected throughout document Corrected 4-Mbit memory addressing tables in Appendices D and E Max ICCD changed to 25 A VCC Max on 32 M (28F320B3) changed to 3.3 V Added 64-Mbit density and faster speed offerings Removed access time vs. capacitance load curve Changed references of 32Mbit 80ns devices to 70ns devices to reflect the faster product offering. Changed VccMax=3.3V reference to indicate the affected product is the 0.25m 32Mbit device. Minor text edits throughout document. Added New Pin-1 indicator information on 40 and 48Lead TSOP packages. Minor text edits throughout document. Added specifications for 0.13 micron product offerings throughout document Minor text edits throughout document. Adjusted ordering information. Adjusted specifications for 0.13 micron product offerings.
-012
-013 -014 -015
-016
Revised and corrected DC Characteristics Table. Adjusted package diagram information. Minor text edits throughout document. Updated ordering information. Adjusted specifications for 0.13 micron product offerings.
-017
Updated AC/DC Characteristics Table. Added TSOP and BGA* package diagram information. Minor text edits throughout document.
-018 -019 -020
Updated the layout of the datasheet. Added line items to Table 34 "Ordering Information: Valid Combinations" on page 70. Removed all x8 products from ordering information, page 70
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1.0
Introduction
This datasheet describes the specifications for the Intel Advanced Boot Block Flash Memory (B3) device (hereafter referred to as the B3 flash memory device). The B3 flash memory device is optimized for portable, low-power, systems. This family of products features 1.65 V to 2.5 V or 2.7 V to 3.6 V I/Os, and a low VCC/V PP operating range of 2.7 V to 3.6 V for Read, Program, and Erase operations. The B3 device is also capable of fast programming at 12 V. Throughout this document:
* 2.7 V refers to the full voltage range 2.7 V to 3.6 V (except where noted otherwise). * VPP = 12 V refers to 12 V 5%.
1.1
Table 1.
Nomenclature
Nomenclature
Term 0x 0b Byte Word KW or Kword Mword Kb KB Mb MB APS CSP CUI OTP PR PRD PLR RFU SR SRD WSM Definition Hexadecimal prefix Binary prefix 8 bits 16 bits 1024 words 1,048,576 words 1024 bits 1024 bytes 1,048,576 bits 1,048,576 bytes Automatic Power Savings Chip Scale Package Command User Interface One Time Programmable Protection Register Protection Register Data Protection Lock Register Reserved for Future Use Status Register Status Register Data Write State Machine
Datasheet
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1.2
Table 2.
Conventions
Conventions
Convention Description Used interchangeably to refer to the external signal connections on the package. Note: Group Membership Brackets Set Clear: Block Main Block Parameter Block For a chip scale package (CSP), the term ball is used in place of pin.
Pin or signal
Square brackets designate group membership or define a group of signals with similar function (for example, A[21:1], SR[4:1]) When referring to registers, the term set means the bit is a logical 1. When referring to registers, the term clear means the bit is a logical 0. A group of bits (or words) that erase simultaneously using one block erase instruction. A block that contains 32 Kwords. A block that contains 4 Kwords.
2.0
Functional Overview
The B3 flash memory device features the following:
* Enhanced blocking for easy segmentation of code and data or additional design flexibility. * Program Suspend to Read command. * VCCQ input of 1.65 V to 2.5 V or 2.7 V to 3.6 V on all I/Os. See Figure 1 through Figure 4 for
pinout diagrams and VCCQ location.
* Maximum program and erase time specification for improved data storage.
Table 3. B3 Device Feature Summary (Sheet 1 of 2)
Feature VCC Read Voltage VCCQ I/O Voltage VPP Program/Erase Voltage Bus Width Speed 8 bit 28F008B3, 28F016B3 2.7 V- 3.6 V 1.65 V-2.5 V or 2.7 V- 3.6 V 2.7 V- 3.6 V or 11.4 V- 12.6 V 16 bit 28F800B3, 28F160B3, 28F320B3(3), 28F640B3 Reference Section 6.2, Section 7.2 Section 4.2, 4.4 Section 4.2, 4.4 Table 27 Section 8.1
70 ns, 80 ns, 90 ns, 100 ns, 110 ns 512 Kbit x 16 (8 Mbit), 1024 Kbit x 16 (16 Mbit), 2048 Kbit x 16 (32 Mbit), 4096 Kbit x 16 (64 Mbit)
Memory Arrangement
1024 Kbit x 8 (8 Mbit), 2048 Kbit x 8 (16 Mbit)
Section 3.2
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Table 3.
B3 Device Feature Summary (Sheet 2 of 2)
Feature 28F008B3, 28F016B3 28F800B3, 28F160B3, 28F320B3(3), 28F640B3 Reference Section 3.2, "Memory Maps and Block Organization" on page 11 Section 12.0 Table 32 Section 6.2, Section 7.2 Section 6.2, Section 7.2 Figure 8, Figure 9
Blocking (top or bottom)
Eight 8-Kbyte parameter blocks and Fifteen 64-Kbyte blocks (8 Mbit) or Thirty-one 64-Kbyte main blocks (16 Mbit) Sixty-three 64-Kbyte main blocks (32 Mbit) One hundred twenty-seven 64-Kbyte main blocks (64 Mbit) WP# locks/unlocks parameter blocks All other blocks protected using VPP Extended: -40 C to +85 C 100,000 cycles 40-lead TSOP(1), 48-Ball BGA* CSP (2) 48-Lead TSOP, 48-Ball BGA CSP(2), 48-Ball VF BGA
Locking Operating Temperature Program/Erase Cycling
Packages
Notes: 1. 32-Mbit and 64-Mbit densities not available in 40-lead TSOP. 2. 8-Mbit densities not available in BGA* CSP. 3. VCC Max is 3.3 V on 0.25m 32-Mbit devices.
3.0
Functional Overview
Intel provides the most flexible voltage solution in the flash industry, providing three discrete voltage supply pins:
* VCC for Read operation * VCCQ for output swing * VPP for Program and Erase operation.
All B3 flash memory devices provide program/erase capability at 2.7 V or 12 V (for fast production programming), and read with V CC at 2.7 V. Because many designs read from the flash memory a large percentage of the time, 2.7 V VCC operation can provide substantial power savings. The B3 flash memory device family is available in either x8 or x16 packages in the following densities (see Appendix C, "Ordering Information," for availability):
* 8-Mbit (8, 388, 608-bit) flash memory organized as 512 Kwords of 16 bits each or 1024
Kbytes of 8-bits each.
* 16-Mbit (16, 777, 216-bit) flash memory organized as 1024 Kwords of 16 bits each or
2048 Kbytes of 8-bits each.
* 32-Mbit (33, 554, 432-bit) flash memory organized as 2048 Kwords of 16 bits each. * 64-Mbit (67, 108, 864-bit) flash memory organized as 4096 Kwords of 16 bits each.
The parameter blocks are located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map, to accommodate different microprocessor protocols for kernel code location. The upper two (or lower two) parameter blocks can be locked to provide complete code security for system initialization code. Locking and unlocking is controlled by Write Protect WP# (see Section 12.0, "Block Locking" on page 62 for details). Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 9
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* The Command User Interface (CUI) is the interface between the microprocessor or
microcontroller and the internal operation of the flash memory.
* The internal Write State Machine (WSM) automatically executes the algorithms and timings
necessary for Program and Erase operations (including verification), which unburdens the microprocessor or microcontroller.
* To indicate the status of the WSM, the Status Register signifies block erase or word program
completion and status. The B3 flash memory device also provides Automatic Power Savings (APS), which minimizes system current drain and allows for very low power designs. This mode is entered following the completion of a read cycle (approximately 300 ns later). The RP# pin provides additional protection against unwanted command writes that might occur during system reset and power-up/down sequences due to invalid system bus conditions (see "Power and Reset Specifications" on page 47).
* Section 10.0, "Operations Overview" on page 50 explains the different modes of operation. * Section 7.0, "Electrical Specifications" on page 34 and Section 8.0, "AC Characteristics" on
page 37 provide complete current and voltage specifications.
* Section 8.1, "AC Read Characteristics" on page 37 provides read, program, and erase
performance specifications.
3.1
Figure 1.
Architecture Diagram
B3 Architecture Block Diagram
DQ0-DQ15
VCCQ Output Buffer Input Buffer
Output Multiplexer
Status Register
Data Register
Identifier Register
I/O Logic Command User Interface CE# WE# OE# RP# WP#
Power Reduction Control A0-A19 Y-Decoder Input Buffer 4-KWord Parameter Block
Data Comparator
Y-Gating/Sensing 4-KWord Parameter Block 32-KWord Main Block
Write State Machine 32-KWord Main Block
Program/Erase Voltage Switch
VPP
Address Latch Address Counter
X-Decoder
VCC GND
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3.2
Memory Maps and Block Organization
The B3 flash memory device uses an asymmetrically blocked architecture, enabling system integration of code and data within a single flash memory device. Each block can be erased independently of other blocks up to 100,000 times. For the address locations of each block, see the following memory maps:
* * * * * 3.2.1
Table 4 "16-Mbit and 32-Mbit Word-Wide Memory Addressing Map" on page 11 Table 5 "4-Mbit and 8-Mbit Word-Wide Memory Addressing Map" on page 14 Table 6 "16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map" on page 15 Table 7 "8-Mbit and 16-Mbit Byte-Wide Memory Addressing Map" on page 20 Table 8 "4-Mbit Byte Wide Memory Addressing Map" on page 23
Parameter Blocks
The B3 flash memory device architecture includes parameter blocks to facilitate storing frequently updated small parameters (such as data traditionally stored in an EEPROM). The word-rewrite functionality of EEPROMs can be emulated using software techniques. Each flash memory device contains eight parameter blocks of 8 Kbytes/4 Kwords (8192 bytes/4,096 words) each.
3.2.2
Main Blocks
After the parameter blocks, the remainder of the flash memory array is divided into equal-size main blocks (65,536 bytes/32,768 words) for data or code storage.
* * * * 3.2.3
Table 4.
The 8-Mbit flash memory device contains 15 main blocks. The 16-Mbit flash memory device contains 31 main blocks. The 32-Mbit memory device contains 63 main blocks. The 64-Mbit memory device contains 127 main blocks.
4-Mbit, 8-Mbit, 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Maps
16-Mbit and 32-Mbit Word-Wide Memory Addressing Map (Sheet 1 of 4)
16-Mbit and 32-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot 32 Mbit 1FF000-1FFFFF 1FE000-1FEFFF 1FD000-1FDFFF 1FC000-1FCFFF Size (KW) 32 32 32 32 8 Mbit 16 Mbit 32 Mbit 1F8000-1FFFFF 1F0000-1F7FFF 1E80001EFFFF 1E00001E7FFF
Size (KW) 4 4 4 4
16 Mbit FF000-FFFFF FE000-FEFFF FD000-FDFFF FC000-FCFFF
Datasheet
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Table 4.
16-Mbit and 32-Mbit Word-Wide Memory Addressing Map (Sheet 2 of 4)
16-Mbit and 32-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot 32 Mbit 1FB000-1FBFFF 1FA000-1FAFFF 1F9000-1F9FFF 1F8000-1F8FFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 F8000-FFFFF F0000-F7FFF 8 Mbit 16 Mbit 32 Mbit 1D80001DFFFF 1D00001D7FFF 1C80001CFFFF 1C00001C7FFF 1B80001BFFFF 1B00001B7FFF 1A80001AFFFF 1A00001A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF 0F0000-0F7FFF
Size (KW) 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
16 Mbit FB000-FBFFF FA000-FAFFF F9000-F9FFF F8000-F8FFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF
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Table 4.
16-Mbit and 32-Mbit Word-Wide Memory Addressing Map (Sheet 3 of 4)
16-Mbit and 32-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot 32 Mbit 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF Size (KW) 32 32 32 32 32 8 Mbit 16 Mbit E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF This column continues on next page 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 0C00000C7FFF 0B80000BFFFF 0B00000B7FFF 0A80000AFFFF 0A00000A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 32 Mbit 0E80000EFFFF 0E00000E7FFF 0D80000DFFFF 0D00000D7FFF 0C80000CFFFF
Size (KW) 32 32 32 32 32
16 Mbit 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 00000-07FFF
This column continues on next page 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 0F8000-0FFFFF 0F0000-0F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF
Datasheet
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 le 4. 16-Mbit and 32-Mbit Word-Wide Memory Addressing Map (Sheet 4 of 4)
16-Mbit and 32-Mbit Word-Wide Memory Addressing Top Boot ize W) 16 Mbit 32 Mbit 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 000000-007FFF Size (KW) 4 4 4 4 4 4 4 4 8 Mbit Bottom Boot 16 Mbit 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF 32 Mbit 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF
Table 5.
4-Mbit and 8-Mbit Word-Wide Memory Addressing Map (Sheet 1 of 2)
4-Mbit and 8-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot Size (KW) 7F000-7FFFF 7E000-7EFFF 7D000-7DFFF 7C000-7CFFF 7B000-7BFFF 7A000-7AFFF 79000-79FFF 78000-78FFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 4 Mbit 8 Mbit 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF
Size (KW)
4 Mbit 3F000-3FFFF 3E000-3EFFF 3D000-3DFFF 3C000-3CFFF 3B000-3BFFF 3A000-3AFFF 39000-39FFF 38000-38FFF
4 4 4 4 4 4 4 4 32 32 32 32
30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 00000-07FFF
18 Aug 2005 14
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
Datasheet
www..com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 5.
4-Mbit and 8-Mbit Word-Wide Memory Addressing Map (Sheet 2 of 2)
4-Mbit and 8-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot Size (KW) 10000-17FFF 08000-0FFFF 00000-07FFF 4 4 4 4 Mbit 02000-02FFF 01000-01FFF 00000-00FFF 8 Mbit 02000-02FFF 01000-01FFF 00000-00FFF
Size (KW) 32 32 32
4 Mbit
Table 6.
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 1 of 6)
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot 64 Mbit 3FF000-3FFFFF 3FE000-3FEFFF 3FD000-3FDFFF 3FC000-3FCFFF 3FB000-3FBFFF 3FA000-3FAFFF 3F9000-3F9FFF 3F8000-3F8FFF 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF 3D8000-3DFFFF 3D0000-3D7FFF 3C8000-3CFFFF 3C0000-3C7FFF 3B8000-3BFFFF Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 Mbit 32 Mbit 64 Mbit 3F80003FFFFF 3F00003F7FFF 3E80003EFFFF 3E00003E7FFF 3D80003DFFFF 3D00003D7FFF 3C80003CFFFF 3C00003C7FFF 3B80003BFFFF 3B00003B7FFF 3A80003AFFFF 3A00003A7FFF 398000-39FFFF 390000-397FFF 388000-38FFFF 380000-387FFF
Size (KW) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32
16 Mbit FF000-FFFFF FE000-FEFFF FD000-FDFFF FC000-FCFFF FB000-FBFFF FA000-FAFFF F9000-F9FFF F8000-F8FFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF B8000-BFFFF
32 Mbit 1FF0001FFFFF 1FE0001FEFFF 1FD0001FDFFF 1FC0001FCFFF 1FB0001FBFFF 1FA0001FAFFF 1F90001F9FFF 1F80001F8FFF 1F00001F7FFF 1E80001EFFFF 1E00001E7FFF 1D80001DFFFF 1D00001D7FFF 1C80001CFFFF 1C00001C7FFF 1B80001BFFFF
Datasheet
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
18 Aug 2005 15
www..com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 6.
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 2 of 6)
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot 64 Mbit 3B0000-3B7FFF 3A8000-3AFFFF 3A0000-3A7FFF 398000-39FFFF 390000-397FFF 388000-38FFFF 380000-387FFF 378000-37FFFF 370000-377FFF 368000-36FFFF 360000-367FFF 358000-35FFFF 350000-357FFF 348000-34FFFF 340000-347FFF 338000-33FFFF 330000-337FFF 328000-32FFFF 320000-327FFF 318000-31FFFF 310000-317FFF Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 Mbit 32 Mbit 64 Mbit 378000-37FFFF 370000-377FFF 368000-36FFFF 360000-367FFF 358000-35FFFF 350000-357FFF 348000-34FFFF 340000-347FFF 338000-33FFFF 330000-337FFF 328000-32FFFF 320000-327FFF 318000-31FFFF 310000-317FFF 308000-30FFFF 300000-307FFF 2F80002FFFFF 2F00002F7FFF 2E80002EFFFF 2E00002E7FFF 2D80002DFFFF
Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
16 Mbit B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF
32 Mbit 1B00001B7FFF 1A80001AFFFF 1A00001A7FFF 19800019FFFF 190000197FFF 18800018FFFF 180000187FFF 17800017FFFF 170000177FFF 16800016FFFF 160000167FFF 15800015FFFF 150000157FFF 14800014FFFF 140000147FFF 13800013FFFF 130000137FFF 12800012FFFF 120000127FFF 118000-11FFFF 110000-117FFF
18 Aug 2005 16
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
Datasheet
www..com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 6.
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 3 of 6)
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot 64 Mbit 308000-30FFFF 300000-307FFF 2F8000-2FFFFF 2F0000-2F7FFF 2E8000-2EFFFF 2E0000-2E7FFF 2D8000-2DFFFF 2D0000-2D7FFF 2C8000-2CFFFF 2C0000-2C7FFF 2B8000-2BFFFF 2B0000-2B7FFF 2A8000-2AFFFF 2A0000-2A7FFF 298000-29FFFF 290000-297FFF 288000-28FFFF 280000-287FFF 278000-27FFFF 270000-277FFF 268000-26FFFF Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 Mbit 32 Mbit 64 Mbit 2D00002D7FFF 2C80002CFFFF 2C00002C7FFF 2B80002BFFFF 2B00002B7FFF 2A80002AFFFF 2A00002A7FFF 298000-29FFFF 290000-297FFF 288000-28FFFF 280000-287FFF 278000-27FFFF 270000-277FFF 268000-26FFFF 260000-267FFF 258000-25FFFF 250000-257FFF 248000-24FFFF 240000-247FFF 238000-23FFFF 230000-237FFF
Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
16 Mbit 08000-0FFFF 00000-07FFF
32 Mbit 10800010FFFF 100000107FFF 0F80000FFFFF 0F00000F7FFF 0E80000EFFFF 0E00000E7FFF 0D80000DFFFF 0D00000D7FFF 0C80000CFFFF 0C00000C7FFF 0B80000BFFFF 0B00000B7FFF 0A80000AFFFF 0A00000A7FFF 09800009FFFF 090000097FFF 08800008FFFF 080000087FFF 07800007FFFF 070000077FFF 06800006FFFF
Datasheet
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
18 Aug 2005 17
www..com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 6.
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 4 of 6)
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot 64 Mbit 260000-267FFF 258000-25FFFF 250000-257FFF 248000-24FFFF 240000-247FFF 238000-23FFFF 230000-237FFF 228000-22FFFF 220000-227FFF 218000-21FFFF 210000-217FFF 208000-21FFFF 200000-207FFF 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 1F80001FFFFF 1F00001F7FFF 1E80001EFFFF 1E00001E7FFF 1D80001DFFFF 1D00001D7FFF 1C80001CFFFF 1C00001C7FFF 1B80001BFFFF 1B00001B7FFF 1A80001AFFFF 1A00001A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 16 Mbit 32 Mbit 64 Mbit 228000-22FFFF 220000-227FFF 218000-21FFFF 210000-217FFF 208000-20FFFF 200000-207FFF 1F80001FFFFF 1F00001F7FFF 1E80001EFFFF 1E00001E7FFF 1D80001DFFFF 1D00001D7FFF 1C80001CFFFF 1C00001C7FFF 1B80001BFFFF 1B00001B7FFF 1A80001AFFFF 1A00001A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF
Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
16 Mbit
32 Mbit 060000067FFF 05800005FFFF 050000057FFF 04800004FFFF 040000047FFF 03800003FFFF 030000037FFF 02800002FFFF 020000027FFF 01800001FFFF 010000017FFF 00800000FFFF 000000007FFF
18 Aug 2005 18
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
Datasheet
www..com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 6.
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 5 of 6)
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot 64 Mbit 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF 0F0000-0F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 F8000-FFFFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 16 Mbit 32 Mbit 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF F8000-FFFFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 64 Mbit 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF F8000-FFFFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF
Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
16 Mbit
32 Mbit
Datasheet
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
18 Aug 2005 19
www..com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 6.
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 6 of 6)
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot 64 Mbit 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 000000-007FFF Size (KW) 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 16 Mbit 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF 32 Mbit 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF 64 Mbit 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF
Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
16 Mbit
32 Mbit
3.2.4
Table 7.
4-Mbit, 8-Mbit, and 16-Mbit Byte-Wide Memory Maps
8-Mbit and 16-Mbit Byte-Wide Memory Addressing Map (Sheet 1 of 3)
8-Mbit and 16-Mbit Byte-Wide Byte-Wide Memory Addressing Top Boot Bottom Boot 16 Mbit 1FE000-1FFFFF 1FC000-1FDFFF 1FA000-1FBFFF 1F8000-1F9FFF 1F6000-1F7FFF 1F4000-1F5FFF 1F2000-1F3FFF 1F0000-1F1FFF Size (KB) 64 64 64 64 64 64 64 64 8 Mbit 16 Mbit
Size (KB) 8 8 8 8 8 8 8 8
8 Mbit FE000-FFFFF FC000-FDFFF FA000-FBFFF F8000-F9FFF F6000-F7FFF F4000-F5FFF F2000-F3FFF F0000-F1FFF
18 Aug 2005 20
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
Datasheet
www..com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 7.
8-Mbit and 16-Mbit Byte-Wide Memory Addressing Map (Sheet 2 of 3)
8-Mbit and 16-Mbit Byte-Wide Byte-Wide Memory Addressing Top Boot Bottom Boot 16 Mbit 1E0000-1EFFFF 1D0000-1DFFFF 1C0000-1CFFFF 1B0000-1BFFFF 1A0000-1AFFFF 190000-19FFFF 180000-18FFFF 170000-17FFFF 160000-16FFFF 150000-15FFFF 140000-14FFFF 130000-13FFFF 120000-12FFFF 110000-11FFFF 100000-10FFFF 0F0000-0FFFFF 0E0000-0EFFFF 0D0000-0DFFFF 0C0000-0CFFFF 0B0000-0BFFFF 0A0000-0AFFFF 090000-09FFFF 080000-08FFFF 070000-07FFFF 060000-06FFFF 050000-05FFFF 040000-04FFFF 030000-03FFFF 020000-02FFFF 010000-01FFFF 000000-00FFFF Size (KB) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 1F0000-1FFFFF 1E0000-1EFFFF 1D0000-1DFFFF 1C0000-1CFFFF 1B0000-1BFFFF 1A0000-1AFFFF 190000-19FFFF 180000-18FFFF 170000-17FFFF 160000-16FFFF 150000-15FFFF 8 Mbit 16 Mbit
Size (KB) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64
8 Mbit E0000-EFFFF D0000-DFFFF C0000-CFFFF B0000-BFFFF A0000-AFFFF 90000-9FFFF 80000-8FFFF 70000-7FFFF 60000-6FFFF 50000-5FFFF 40000-4FFFF 30000-3FFFF 20000-2FFFF 10000-1FFFF 00000-0FFFF
Datasheet
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
18 Aug 2005 21
www..com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 7.
8-Mbit and 16-Mbit Byte-Wide Memory Addressing Map (Sheet 3 of 3)
8-Mbit and 16-Mbit Byte-Wide Byte-Wide Memory Addressing Top Boot Bottom Boot 16 Mbit Size (KB) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 8 8 8 8 8 8 8 8 F0000-FFFFF E0000-EFFFF D0000-DFFFF C0000-CFFFF B0000-BFFFF A0000-AFFFF 90000-9FFFF 80000-8FFFF 70000-7FFFF 60000-6FFFF 50000-5FFFF 40000-4FFFF 30000-3FFFF 20000-2FFFF 10000-1FFFF 0E000-0FFFF 0C000-0DFFF 0A000-0BFFF 08000-09FFF 06000-07FFF 04000-05FFF 02000-03FFF 00000-01FFF 8 Mbit 16 Mbit 140000-14FFFF 130000-13FFFF 120000-12FFFF 110000-11FFFF 100000-10FFFF 0F0000-0FFFFF 0E0000-0EFFFF 0D0000-0DFFFF 0C0000-0CFFFF 0B0000-0BFFFF 0A0000-0AFFFF 090000-09FFFF 080000-08FFFF 070000-07FFFF 060000-06FFFF 050000-05FFFF 040000-04FFFF 030000-03FFFF 020000-02FFFF 010000-01FFFF 00E000-00FFFF 00C000-00DFFF 00A000-00BFFF 008000-009FFF 006000-007FFF 004000-005FFF 002000-003FFF 000000-001FFF
Size (KB) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64
8 Mbit
18 Aug 2005 22
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
Datasheet
www..com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 8.
4-Mbit Byte Wide Memory Addressing Map
4-Mbit Byte-Wide Memory Addressing Top Boot Bottom Boot Size (KB) 64 64 64 64 64 64 64 8 8 8 8 8 8 8 8 4 Mbit 70000-7FFFF 60000-6FFFF 50000-5FFFF 40000-4FFFF 30000-3FFFF 20000-2FFFF 10000-1FFFF 0E000-0FFFF 0C000-0DFFF 0A000-0BFFF 08000-09FFF 06000-07FFF 04000-05FFF 02000-03FFF 00000-01FFF
Size (KB) 8 8 8 8 8 8 8 8 64 64 64 64 64 64 64
4 Mbit 7E000-7FFFF 7C000-7DFFF 7A000-7BFFF 78000-79FFF 76000-77FFF 74000-75FFF 72000-73FFF 70000-71FFF 60000-6FFFF 50000-5FFFF 40000-4FFFF 30000-3FFFF 20000-2FFFF 10000-1FFFF 00000-0FFFF
Datasheet
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
18 Aug 2005 23
www..com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.0
4.1
Package Information
BGA* and Very Thin Profile Fine Pitch Ball Grid Array (VF BGA) Package
BGA* and VF BGA Package Drawing
Ball A1 Corner
Figure 2.
D
S1
Ball A1 Corner
1
A B
2
3
4
5
6
7
8
A B C D E F
8
7
6
5
4
3
2
1
S2
E
C D E F
e
b
Top View - Bump Side down
Bottom View -Bump side up
A 1 A2 A Seating Plan
Y
Side View
Note: Drawing not to scale
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length 8M (.25) Package Body Length 16M (.25/.18/.13) 32M (.25/.18/.13) Package Body Length 64M (.18) Package Body Width 8M (.25) Package Body Width 16M (.25/.18/.13) 32M (.18/.13) Package Body Width 32M (.25) Package Body Width 64M (.18) Pitch Ball (Lead) Count 8M, 16M Ball (Lead) Count 32M Ball (Lead) Count 64M Seating Plane Coplanarity Corner to Ball A1 Distance Along D 8M (.25) Corner to Ball A1 Distance Along D 16M (.25/.18/.13) 32M (.18/.13) Corner to Ball A1 Distance Along D 64M (.18) Corner to Ball A1 Distance Along E 8M (.25) Corner to Ball A1 Distance Along E 16M (.25/.18/.13) 32M (.18/.13) Corner to Ball A1 Distance Along E 32M (.25) Corner to Ball A1 Distance Along E 64M (.18)
Symbol A A1 A2 b D D D E E E E e N N N Y S1 S1 S1 S2 S2 S2 S2
Min 0.150 0.325 7.810 7.186 7.600 6.400 6.864 10.750 8.900
Millimeters Nom Max 1.000 0.665 0.375 7.910 7.286 7.700 6.500 6.964 10.850 9.000 0.750 46 47 48 1.330 1.018 1.225 1.375 1.607 3.550 2.625
Min 0.0059
Inches Nom
Max 0.0394
0.425 8.010 7.386 7.800 6.600 7.064 10.860 9.100
0.0128 0.2829 0.2992 0.2520 0.2702 0.4232 0.3504
0.0262 0.0148 0.2868 0.3031 0.2559 0.2742 0.4272 0.3543 0.0295 46 47 48 0.0524 0.0401 0.0482 0.0541 0.0633 0.1398 0.1033
0.0167 0.2908 0.3071 0.2598 0.2781 0.4276 0.3583
1.230 0.918 1.125 1.275 1.507 3.450 2.525
0.100 1.430 1.118 1.325 1.475 1.707 3.650 2.725
0.0484 0.0361 0.0443 0.0502 0.0593 0.1358 0.0994
0.0039 0.0563 0.0440 0.0522 0.0581 0.0672 0.1437 0.1073
18 Aug 2005 24
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
Datasheet
www..com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.2
Figure 3.
TSOP Package
TSOP Package Drawing
Z
See Notes 1, 2, 3 and 4
Pin 1
A2
e E See Detail B
Y
D1 D
A1 Seating Plane
See Det ail A
A
Det ail A Detail B
C
b L
0
A5568- 02
Dimensions
Family: Thin Small Out -Line Package Symbol Min Package Height Standoff Package Body Thickness Lead Width Lead Thickness Plastic Body Length Package Body Width Lead Pitch Terminal Dimension Lead Tip Length Lead Count Lead Tip Angle Seating Plane Coplanarity Lead to Package Offset A A1 A2 b c D1 E e D L N O Y Z 0.150 0.250 0 0.050 0.950 0.150 0.100 1.000 0.200 0.150 1.050 0.300 0.200 Millimeters Nom Max 1.200 0.002 0.037 0.006 0.004 0.717 0.465 0.039 0.008 0.006 0.724 0.472 0.0197 0.780 0.020 0.787 0.024 48 5 0.100 0.350 0.006 0.010 0 3 5 0.004 0.014 0.795 0.028 0.041 0.012 0.008 0.732 0.480 Notes Min Inches Nom Max 0.047 Notes
18.200 18.400 18.600 11.800 12.000 12.200 0.500 19.800 20.000 20.200 0.500 0.600 48 3 0.700
Notes: 1. One dimple on package denotes Pin 1. 2. If two dimples, then the larger dimple denotes Pin 1. 3. Pin 1 is in the upper left corner of the package, in reference to the product mark.
Datasheet
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
18 Aug 2005 25
www..com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.3
Figure 4.
Easy BGA Package
Easy BGA Package Drawing
Ball A1 Corner Ball A1 Corner
D
S1
1 A B C D E E F G H
2
3
4
5
6
7
8 A B C D E F G
8
7
6
5
4
3
2
1
S2
b
e H
Top View - Ball side down
Bottom View - Ball Side Up
A1 A2 A
Seating Plane
Y
Note: Drawing not to scale
Side View
Dimensions Table
Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E Symbol A A1 A2 b D E [e] N Y S1 S2 Millimeters Min Nom 0.250 0.330 9.900 12.900 0.780 0.430 10.000 13.000 1.000 64 1.500 3.000 0.530 10.100 13.100 Max 1.200 Notes Inches Min 0.0098 0.0130 0.3898 0.5079 0.0307 0.0169 0.3937 0.5118 0.0394 64 0.0591 0.1181 0.0209 0.3976 0.5157 Nom Max 0.0472
1 1
1.400 2.900
0.100 1.600 3.100
1 1
0.0551 0.1142
0.0039 0.0630 0.1220
Note: (1) Package dimensions are for reference only. These dimensions are estimates based on die size, and are subject to change.
18 Aug 2005 26
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
Datasheet
www..com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
5.0
Pinout and Signal Descriptions
This section explains the package pinout and signal descriptions.
5.1
Signal Pinouts
The B3 flash memory device is available in the following packages:
* * * * 5.1.1
Figure 5.
40-lead TSOP (x8, Figure 5). 48-lead TSOP (x16, Figure 6). 48-ball BGA (x8 in Figure 8 and x16 in Figure 9). 48-ball VF BGA (x16, Figure 9).
40-Lead and 48-Lead TSOP Packages
40-Lead TSOP Package for x8 Configurations
A16 A15 A14 A13 A12 A11 A9 A8 WE# RP# VPP WP# A18 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A17 GND A20 A19 A10 DQ7 DQ6 DQ5 DQ4 VCCQ VCC NC DQ3 DQ2 DQ1 DQ0 OE# GND CE# A0
16 M 8M
Advanced Boot Block 40-Lead TSOP 10 mm x 20 mm TOP VIEW
4M
Notes: 1. 40-Lead TSOP available for 8-Mbit and 16-Mbit densities only. 2. Lower densities have NC on the upper address pins. For example, an 8-Mbit device has NC on Pin 38.
Datasheet
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
18 Aug 2005 27
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 6.
48-Lead TSOP Package for x16 Configurations
A15 A14 A13 A12 A11 A10 A9 A8 A21 A20 WE# RP# VPP WP# A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 VCCQ GND DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# GND CE# A0
64 M 32 M
Advanced Boot Block 48-Lead TSOP 12 mm x 20 mm TOP VIEW
16 M
Figure 7.
New Mark for Pin-1 Indicator: 40-Lead 8/16 Mb TSOP and 48-Lead 8/16/32 Mb TSOP
New Mark:
Note:
The topside marking on 8-Mb, 16-Mb, and 32-Mb Intel Advanced Boot Block 40L and 48L TSOP products changed to a white ink triangle as a Pin-1 indicator. Products without the white triangle continue to use a dimple as a Pin-1 indicator. No other changes were made in package size, materials, functionality, customer handling, or manufacturability. The product continues to meet stringent Intel quality requirements. Table 9 lists the ordering codes of the affected products. See also Table 34 "Ordering Information: Valid Combinations" on page 70.
18 Aug 2005 28
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
(R)
Datasheet
www..com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 9.
B3 Flash Memory Device Ordering Information
Ordering Information Valid Combinations 40-Lead TSOP 48-Lead TSOP
Ext. Temp. 64 Mbit
TE28F640B3TC70 TE28F320B3TD70 TE28F320B3TC70
TE28F640B3BC70 TE28F320B3BD70 TE28F320B3BC70 TE28F320B3BC90 TE28F320B3BA100 TE28F320B3BA110 TE28F160B3BC70 TE28F160B3BC80 TE28F160B3BA90 TE28F160B3BA110 TE28F800B3BA90 TE28F800B3BA110
Ext. Temp. 32 Mbit
TE28F320B3TC90 TE28F320B3TA100 TE28F320B3TA110 TE28F160B3TC70
Ext. Temp. 16 Mbit
TE28F160B3TC80 TE28F016B3TA90 TE28F016B3TA110 TE28F016B3BA90 TE28F016B3BA110 TE28F008B3BA90 TE28F008B3BA110 TE28F160B3TA90 TE28F160B3TA110 TE28F800B3TA90 TE28F800B3TA110
Ext. Temp. 8 Mbit
TE28F008B3TA90 TE28F008B3TA110
Figure 8.
x8 48-Ball BGA* Chip Size Package (Top View, Ball Down)
1 2 3 4 5
16M
6
7
8
A
A14
A12
A8
V PP 8M
W P#
A20
A7
A4
B
A15
A10
WE#
RP#
A19
A18
A5
A2
C
A16
A13
A9
A6
A3
A1
D
A17
NC
D5
NC
D2
NC
CE#
A0
E
VCCQ
A11
D6
NC
D3
NC
D0
GND
F
GND
D7
NC
D4
V CC
NC
D1
OE#
Notes: 1. A19 and A20 indicate the upgrade address connections. Lower density devices do not have the upper address solder balls. Do not route is not done in this area. A20 is the upgrade address for the 16-Mbit device.
Datasheet
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
18 Aug 2005 29
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 9.
x16 48-Ball VF BGA and BGA* Chip Size Package (Top View, Ball Down)
1 2 3 4 5 16M A A13 A11 A8 VPP WP# A19 A7 A4 6 7 8
B
A14
A10
WE# 64M
RP# 32M A21
A18
A17
A5
A2
C
A15
A12
A9
A20
A6
A3
A1
D
A16
D14
D5
D11
D2
D8
CE#
A0
E
VCCQ
D15
D6
D12
D3
D9
D0
Vss
F
Vss
D7
D13
D4
VCC
D10
D1
OE#
Notes: 1. A19, A20, and A21 indicate the upgrade address connections. Lower density devices do not have the upper address solder balls. Do not route in this area. - A19 is the upgrade address for the 16-Mbit device. - A20 is the upgrade address for the 32-Mbit device. - A21 is the upgrade address for the 64-Mbit device. 2. Table 10 "B3 Flash memory Device Signal Descriptions" on page 31 details the usage of each device pin.
5.2
Signal Descriptions
Table 10 describes the active signals.
18 Aug 2005 30
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
Datasheet
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 10.
Symbol
B3 Flash memory Device Signal Descriptions (Sheet 1 of 2)
Type Description ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or erase cycle. 28F008B3: A[0-19], 28F016B3: A[0-20], 28F800B3: A[0-18], 28F160B3: A[0-19], 28F320B3: A[0-20], 28F640B3: A[0-21] DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. * Inputs commands to the Command User Interface when CE# and WE# are active. Data is internally latched. * Outputs array, identifier and Status Register data. The data pins float to tristate when the chip is deselected or the outputs are disabled. DATA INPUTS/OUTPUTS:
A0-A21
Input
DQ0-DQ7
Input/ Output
DQ8-DQ15
Input/ Output
* Inputs array data on the second CE# and WE# cycle during a Program command. Data is internally latched. * Outputs array and identifier data. The data pins float to tristate when the chip is de-selected. Not included on x8 products.
CHIP ENABLE: Activates the internal control logic, input buffers, decoders, and sense amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels. OUTPUT ENABLE: Enables the flash memory device outputs through the data buffers during a Read operation. OE# is active low. WRITE ENABLE: Controls writes to the Command Register and memory array. WE# is active low. Addresses and data are latched on the rising edge of the second WE# pulse. RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to control reset/deep powerdown mode. * When RP# is at logic low, the flash memory device is in reset/deep power-down mode, which drives the outputs to High-Z, resets the Write State Machine, and minimizes current levels (ICCD). * When RP# is at logic high, the flash memory device is in standard operation. When RP# transitions from logic-low to logic-high, the flash memory device defaults to the read array mode. WRITE PROTECT: Locks and unlocks the two lockable parameter blocks.
CE#
Input
OE# WE#
Input Input
RP#
Input
WP#
Input
* When WP# is at logic low, the lockable blocks are locked, preventing Program and Erase operations to those blocks. If a Program or Erase operation is attempted on a locked block, SR.1 and either SR.4 [program] or SR.5 [erase] are set to indicate the operation failed. * When WP# is at logic high, the lockable blocks are unlocked and can be programmed or erased. See Section 12.0, "Block Locking" on page 62 for details on write protection.
OUTPUT V CC: Enables all outputs to be driven to 1.8 V to 2.5 V while the VCC is at 2.7 V to 3.3 V. If the VCC is regulated to 2.7 V to 2.85 V, VCCQ can be driven at 1.65 V to 2.5 V to achieve lowest power operation (see Section 7.2, "DC Voltage Characteristics" on page 36). This input can be tied directly to VCC (2.7 V to 3.6 V). DEVICE Power Supply: 2.7 V to 3.6 V
VCCQ
Input
VCC
Power
Datasheet
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
18 Aug 2005 31
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 10.
Symbol
B3 Flash memory Device Signal Descriptions (Sheet 2 of 2)
Type Description PROGRAM/ERASE Power Supply: Supplies power for Program and Erase operations. VPP can be the same as VCC (2.7 V to 3.6 V) for single supply voltage operation. For fast programming at manufacturing, 11.4 V to 12.6 V can be supplied to VPP. This pin cannot be left floating. 11.4 V to 12.6 V can be applied to VPP only for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP can be connected to 12 V for a total of 80 hours maximum (see Section 13.0, "VPP Program and Erase Voltages" on page 63 for details). VPP < VPPLK protects memory contents against inadvertent or unintended program and erase commands. Ground: For all internal circuitry. All ground inputs must be connected. No Connect: Pin can be driven or left floating.
VPP
Power
GND NC
-- --
6.0
6.1
Warning:
Maximum Ratings and Operating Conditions
Absolute Maximum Ratings
Stressing the flash memory device beyond the Absolute Maximum Ratings in Table 11 can cause permanent damage. These ratings are stress ratings only.
NOTICE: Specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design.
Table 11.
Absolute Maximum Ratings
Parameter Maximum Rating Notes
Extended Operating Temperature During Read During Block Erase and Program Temperature under Bias Storage Temperature Voltage On Any Pin (except VCC and VPP) with Respect to GND VPP Voltage (for Block Erase and Program) with Respect to GND VCC and VCCQ Supply Voltage with Respect to GND Output Short Circuit Current -40 C to +85 C -40 C to +85 C -40 C to +85 C -65 C to +125 C -0.5 V to +3.7 V -0.5 V to +13.5 V -0.2 V to +3.6 V 100 mA 4 1 1,2,3
Notes: 1. Minimum DC voltage is -0.5 V on input/output pins. During transitions, this level might undershoot to -2.0 V for periods <20 ns. Maximum DC voltage on input/output pins is VCC +0.5 V which, during transitions, might overshoot to VCC +2.0 V for periods <20 ns. 2. Maximum DC voltage on VPP might overshoot to +14.0 V for periods <20 ns. 3. VPP Program voltage is typically 1.65 V to 3.6 V. Connection to a 11.4 V to 12.6 V supply can be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. VPP can be connected to 12 V for a total of 80 hours maximum. 4. Output shorted for no more than one second. No more than one output shorted at a time.
18 Aug 2005 32
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
Datasheet
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
6.2
Operating Conditions
Do not operate the flash memory device beyond the Operating Conditions in Table 12. Extended exposure beyond the Operating Conditions can affect device reliability.
Table 12.
Temperature and Voltage Operating Conditions
Symbol Parameter Min Max Units Notes
TA VCC1 VCC2 VCCQ1 VCCQ2 VCCQ3 VPP1 VPP2 Cycling
Operating Temperature VCC Supply Voltage
-40 2.7 3.0 2.7
+85 3.6 3.6 3.6 2.5 2.5 3.6 12.6
C Volts 1, 2 1, 2 1 Volts
I/O Supply Voltage
1.65 1.8
Supply Voltage
1.65 11.4
Volts Volts Cycles
1 1, 3 3
Block Erase Cycling
100,000
Notes: 1. VCC and VCCQ must share the same supply when they are in the VCC1 range. 2. VCCMax = 3.3 V for 0.25m 32-Mbit devices. 3. VPP = 11.4 V-12.6 V can be applied during a program/erase only for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP can be connected to 12 V for a total of 80 hours maximum.
Datasheet
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
18 Aug 2005 33
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
7.0
7.1
Table 13.
Electrical Specifications
DC Current Characteristics
DC Current Characteristics (Sheet 1 of 2)
VCC 2.7 V-3.6 V 2.7 V-3.6 V Typ Max 1 2.7 V-2.85 V 1.65 V-2.5 V Typ Max 1 2.7 V-3.3 V 1.8 V-2.5 V Typ Max 1 Unit Test Conditions
Sym
Parameter
VCCQ Note
ILI
Input Load Current
1,2
A
VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or GND VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or GND VCC = VCCMax CE# = RP# = VCCQ or during Program/ Erase Suspend WP# = VCCQ or GND VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or GND RP# = GND 0.2 V VCC = VCCMax VCCQ = VCCQMax OE# = VIH, CE# =VIL f = 5 MHz, IOUT=0 mA Inputs = VIL or VIH RP# = GND 0.2 V VPP VCC VPP =VPP1, Program in Progress VPP = VPP2 (12v) Program in Progress VPP = VPP1, Erase in Progress VPP = VPP2 (12v) , Erase in Progress
ILO
Output Leakage Current VCC Standby Current for 0.13 and 0.18 Micron Product VCC Standby Current for 0.25 Micron Product VCC Power-Down Current for 0.13 and 0.18 Micron Product VCC Power-Down Current for 0.25 Product VCC Read Current for 0.13 and 0.18 Micron Product VCC Read Current for 0.25 Micron Product
1,2
10
10
10
A
1
7
15
20
50
150
250
A
ICCS
1
10
25
20
50
150
250
A
1,2
7
15
7
20
7
20
A
ICCD
1,2
7
25
7
25
7
25
A
1,2,3
9
18
8
15
9
15
mA
ICCR
1,2,3 1
10 0.2 18
18 5 55 22 45 15
8 0.2 18 10 21 16
15 5 55 30 45 45
9 0.2 18 10 21 16
15 5 55 30 45 45
mA A mA mA mA mA
IPPD
VPP Deep Power-Down Current
ICCW
VCC Program Current
1,4 8 16
ICCE
VCC Erase Current
1,4 8
ICCES/ ICCWS
VCC Erase Suspend Current for 0.13 and 0.18 Micron Product 1,4,5 VCC Erase Suspend Current for 0.25 Micron Product VPP Read Current 1,4
7
15
50
200
50
200
A CE# = VIH, Erase Suspend in Progress
10 2
25
15
50 2 50
200
15
50 2 50
200
15
A A A VPP VCC VPP > VCC
IPPR
50
200
200
200
18 Aug 2005 34
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
Datasheet
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 13.
DC Current Characteristics (Sheet 2 of 2)
VCC 2.7 V-3.6 V 2.7 V-3.6 V Typ Max 2.7 V-2.85 V 1.65 V-2.5 V Typ Max 2.7 V-3.3 V 1.8 V-2.5 V Typ Max Unit Test Conditions
Sym
Parameter
VCCQ Note
0.05 IPPW VPP Program Current 1,4 8 0.05 IPPE VPP Erase Current 1,4 8
0.1 22 0.1 22
0.05 8 0.05 16
0.1 22 0.1 45
0.05 8 0.05 16
0.1 22 0.1 45
mA mA mA mA
VPP =VPP1, Program in Progress VPP = VPP2 (12v) Program in Progress VPP = VPP1, Erase in Progress VPP = VPP2 (12v) , Erase in Progress VPP = VPP1, Program or Erase Suspend in Progress VPP = VPP2 (12v) , Program or Erase Suspend in Progress
0.2 IPPES/ IPPWS VCC Erase Suspend Current 1,4 50
5
0.2
5
0.2
5
A
200
50
200
50
200
A
Notes: 1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA = +25 C. 2. The test conditions VCCMax, VCCQMax, VCCMin, and VCCQMin refer to the maximum or minimum VCC or VCCQ voltage listed at the top of each column. VCCMax = 3.3 V for 0.25m 32-Mbit devices. 3. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS inputs). 4. Sampled, not 100% tested. 5. ICCES or ICCWS is specified with the flash memory device deselected. - If the device is read while in erase suspend, the current draw is the sum of ICCES and ICCR. - If the device is read while in program suspend, the current draw is the sum of ICCWS and ICCR.
Datasheet
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
18 Aug 2005 35
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
7.2
Table 14.
DC Voltage Characteristics
DC Voltage Characteristics
VCC 2.7 V-3.6 V 2.7 V-3.6 V Min Max 2.7 V-2.85 V 1.65 V-2.5 V Min Max 2.7 V-3.3 V 1.8 V-2.5 V Min Max Unit Test Conditions
Symbol
Parameter
VCCQ Note
VIL VIH VOL
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPP LockOut Voltage VPP During Program / Erase Operations VCC Prog/ Erase Lock Voltage VCCQ Prog/ Erase Lock Voltage 1 1 1,2
-0.4 2.0
VCC * 0.22 V VCCQ +0.3V 0.1
-0.4 VCCQ - 0.4V -0.1
0.4 VCCQ +0.3V 0.1
-0.4 VCCQ - 0.4V -0.1
0.4 VCCQ +0.3V 0.1
V V VCC = VCCMin VCCQ = VCCQMin IOL = 100 A VCC = VCCMin VCCQ = VCCQMin IOH = -100 A Complete Write Protection
-0.1
V
VOH VPPLK VPP1 VPP2
VCCQ -0.1V 1.0 1.65 11.4 3.6 12.6
VCCQ - 0.1V 1.0 1.65 11.4 3.6 12.6
VCCQ - 0.1V 1.0 1.65 11.4 3.6 12.6
V
V V V
VLKO
1.5
1.5
1.5
V
VLKO2
1.2
1.2
1.2
V
Notes: 1. Erase and Program are inhibited when VPP < VPPLK and not guaranteed outside the valid VPP ranges of VPP1 and VPP2. 2. VPP = 11.4 V-12.6 V can be applied during program/erase only for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP can be connected to 12 V for a total of 80 hours maximum.
18 Aug 2005 36
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
Datasheet
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
8.0
8.1
Table 15.
AC Characteristics
AC Read Characteristics
Read Operations--8-Mbit Density
Density Product 90 ns 3.0 V - 3.6 V Min Max 2.7 V - 3.6 V Min Max 8 Mbit 110 ns Unit VCC Note 3.0 V - 3.6 V Min Max 2.7 V - 3.6 V Min Max
#
Sym
Parameter
R1 R2 R3 R4 R5 R6 R7 R8 R9
tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tOH
Read Cycle Time Address to Output Delay CE# to Output Delay OE# to Output Delay RP# to Output Delay CE# to Output in Low Z OE# to Output in Low Z CE# to Output in High Z OE# to Output in High Z Output Hold from Address, CE#, or OE# Change, Whichever Occurs First
3,4 3,4 1,3,4 1,3,4 3,4 2,3,4 2,3,4 2,3,4 2,3,4
80 80 80 30 150 0 0 20 20
90 90 90 30 150 0 0 20 20
100 100 100 30 150 0 0 20 20
110 110 110 30 150 0 0 20 20
ns ns ns ns ns ns ns ns ns
R10
2,3,4
0
0
0
0
ns
Notes: 1. 2. 3. 4.
OE# can be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. Sampled, but not 100% tested. See Figure 10 "Read Operation Waveform" on page 40. See Figure 12 "AC Input/Output Reference Waveform" on page 46 for timing measurements and maximum allowable input slew rate.
Datasheet
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
18 Aug 2005 37
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 16.
Read Operations--16-Mbit Density
Density Product 70 ns 2.7 V-3.6 V Min Max 80 ns 2.7 V-3.6 V Min Max 16 Mbit 90 ns 3.0 V-3.6 V Min Max 2.7 V-3.6 V Min Max 3.0 V- 3.6V Min Max 110 ns Unit 2.7 V-3.6V Min Max Notes
#
Sym
Param eter
VCC
R1 R2 R3 R4 R5 R6 R7 R8 R9
tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ
Read Cycle Time Address to Output Delay CE# to Output Delay OE# to Output Delay RP# to Output Delay CE# to Output in Low Z OE# to Output in Low Z CE# to Output in High Z OE# to Output in High Z Output Hold from Address, CE#, or OE# Change, Whichever Occurs First
70 70 70 20 150 0 0 20 20
80 80 80 20 150 0 0 20 20
80 80 80 30 150 0 0 20 20
90 90 90 30 150 0 0 20 20
100 100 100 30 150 0 0 20 20
110 110 110 30 150 0 0 20 20
ns ns ns ns ns ns ns ns ns
3,4 3,4 1,3,4 1,3,4 3,4 2,3,4 2,3,4 2,3,4 2,3,4
R10
tOH
0
0
0
0
0
0
ns
2,3,4
Notes: 1. 2. 3. 4.
OE# can be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. Sampled, but not 100% tested. See Figure 10 "Read Operation Waveform" on page 40. See Figure 12 "AC Input/Output Reference Waveform" on page 46 for timing measurements and maximum allowable input slew rate.
18 Aug 2005 38
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
Datasheet
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 17.
Read Operations--32-Mbit Density
Density Product 70 ns 2.7 V-3.6 V Min Max 90 ns 2.7 V-3.6 V Min Max 32 Mbit 100 ns 3.0 V-3.3 V Min Max 2.7 V-3.3 V Min Max 110 ns 3.0 V-3.3 V Min Max 2.7 V-3.3 V Min Max Unit Notes
#
Sym
Param eter
VCC
R1 R2 R3 R4 R5 R6 R7 R8 R9
tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ
Read Cycle Time Address to Output Delay CE# to Output Delay OE# to Output Delay RP# to Output Delay CE# to Output in Low Z OE# to Output in Low Z CE# to Output in High Z OE# to Output in High Z Output Hold from Address, CE#, or OE# Change, Whichever Occurs First
70 70 70 20 150 0 0 20 20
90 90 90 20 150 0 0 20 20
90 90 90 30 150 0 0 20 20
100 100 100 30 150 0 0 20 20
100 100 100 30 150 0 0 20 20
110 110 110 30 150 0 0 20 20
ns ns ns ns ns ns ns ns ns
3,4 3,4 1,3,4 1,3,4 3,4 2,3,4 2,3,4 2,3,4 2,3,4
R10
tOH
0
0
0
0
0
0
ns
2,3,4
Notes: 1. 2. 3. 4.
OE# can be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. Sampled, but not 100% tested. See Figure 10 "Read Operation Waveform" on page 40. See Figure 12 "AC Input/Output Reference Waveform" on page 46 for timing measurements and maximum allowable input slew rate.
Datasheet
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 18.
Read Operations -- 64-Mbit Density
Density Product # Sym Parameter VCC Note 2.7 V-3.6 V Min Max 2.7 V-3.6 V Min Max 70 ns 64 Mbit 80 ns Unit
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10
Notes: 1. 2. 3. 4.
tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tOH
Read Cycle Time Address to Output Delay CE# to Output Delay OE# to Output Delay RP# to Output Delay CE# to Output in Low Z OE# to Output in Low Z CE# to Output in High Z OE# to Output in High Z Output Hold from Address, CE#, or OE# Change, Whichever Occurs First
3,4 3,4 1,3,4 1,3,4 3,4 2,3,4 2,3,4 2,3,4 2,3,4 2,3,4
70 70 70 20 150 0 0 20 20 0
80 80 80 20 150 0 0 20 20 0
ns ns ns ns ns ns ns ns ns ns
OE# can be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. Sampled, but not 100% tested. See Figure 10 "Read Operation Waveform" on page 40. See Figure 12 "AC Input/Output Reference Waveform" on page 46 for timing measurements and maximum allowable input slew rate.
Figure 10.
Read Operation Waveform
R1 R2 Address [A] R3 CE# [E] R4 OE# [G] WE# [W] R7 R6 Data [D/Q] R5 RST# [P] R10 R9 R8
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Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
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8.2
Table 19.
AC Write Characteristics
Write Operations--8-Mbit Density
Density Product # Sym Parameter VCC 2.7 V - 3.6 V Note Min 90 Min Min 110 Min 3.0 V - 3.6 V 80 90 ns 8 Mbit 110 ns 100 Unit
W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14
tPHWL / tPHEL tELWL / tWLEL tWLWH / tELEH tDVWH / tDVEH tAVWH / tAVEH tWHEH / tEHWH tWHDX / tEHDX tWHAX / tEHAX tWHWL / tEHEL tVPWH / tVPEH tQVVL tBHWH / tBHEH tQVBL tWHGL
RP# High Recovery to WE# (CE#) Going Low CE# (WE#) Setup to WE# (CE#) Going Low WE# (CE#) Pulse Width Data Setup to WE# (CE#) Going High Address Setup to WE# (CE#) Going High CE# (WE#) Hold Time from WE# (CE#) High Data Hold Time from WE# (CE#) High Address Hold Time from WE# (CE#) High WE# (CE#) Pulse Width High VPP Setup to WE# (CE#) Going High VPP Hold from Valid SRD WP# Setup to WE# (CE#) Going High WP# Hold from Valid SRD WE# High to OE# Going Low
4,5 4,5 4,5 2,4,5 2,4,5 4,5 2,4,5 2,4,5 2,4,5 3,4,5 3,4 3,4 3,4 3,4
150 0 50 50 50 0 0 0 30 200 0 0 0 30
150 0 60 50 60 0 0 0 30 200 0 0 0 30
150 0 70 60 70 0 0 0 30 200 0 0 0 30
150 0 70 60 70 0 0 0 30 200 0 0 0 30
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). So tWP = tWLWH = tELEH = tWLEH = tELWH.
2. 3. 4. 5.
Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). So tWPH = tWHWL = tEHEL = tWHEL = tEHWL. Refer to Table 27 "Bus Operations(1)" on page 51 for valid AIN or DIN. Sampled, but not 100% tested. See Figure 12 "AC Input/Output Reference Waveform" on page 46 for timing measurements and maximum allowable input slew rate. See Figure 11 "Write Operations Waveform" on page 45.
Datasheet
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 20.
Write Operations--16-Mbit Density
Density Product 70 ns 80 ns 16 Mbit 90 ns 80 70 Min 80 Min Min 90 Min Min 110 ns 100 110 Min Unit
#
Sym
Parameter VCC
3.0 V - 3.6 V 2.7 V - 3.6 V Note
W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14
tPHWL / tPHEL tELWL / tWLEL tWLWH / tELEH tDVWH / tDVEH tAVWH / tAVEH tWHEH / tEHWH tWHDX / tEHDX tWHAX / tEHAX tWHWL / tEHEL tVPWH / tVPEH tQVVL tBHWH / tBHEH tQVBL tWHGL
RP# High Recovery to WE# (CE#) Going Low CE# (WE#) Setup to WE# (CE#) Going Low WE# (CE#) Pulse Width Data Setup to WE# (CE#) Going High Address Setup to WE# (CE#) Going High CE# (WE#) Hold Time from WE# (CE#) High Data Hold Time from WE# (CE#) High Address Hold Time from WE# (CE#) High WE# (CE#) Pulse Width High VPP Setup to WE# (CE#) Going High VPP Hold from Valid SRD WP# Setup to WE# (CE#) Going High WP# Hold from Valid SRD WE# High to OE# Going Low
4,5 4,5 1,4,5 2,4,5 2,4,5 4,5 2,4,5 2,4,5 1,4,5 3,4,5 3,4 3,4 3,4 3,4
150 0 45 40 50 0 0 0 25 200 0 0 0 30
150 0 50 40 50 0 0 0 30 200 0 0 0 30
150 0 50 50 50 0 0 0 30 200 0 0 0 30
150 0 60 50 60 0 0 0 30 200 0 0 0 30
150 0 70 60 70 0 0 0 30 200 0 0 0 30
150 0 70 60 70 0 0 0 30 200 0 0 0 30
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). So tWP = tWLWH = tELEH = tWLEH = tELWH.
2. 3. 4. 5.
Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). So tWPH = tWHWL = tEHEL = tWHEL = tEHWL. Refer to Table 27 "Bus Operations(1)" on page 51 for valid AIN or DIN. Sampled, but not 100% tested. See Figure 12 "AC Input/Output Reference Waveform" on page 46 for timing measurements and maximum allowable input slew rate. See Figure 11 "Write Operations Waveform" on page 45.
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Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
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Table 21.
Write Operations--32-Mbit Density
Density Product 70 ns 90 ns 90 70 Min 90 Min Min 100 Min Min 32 Mbit 100 ns 110 ns 100 110 Min Unit
#
Sym
Parameter VCC
3.0 V - 3.6 V6 2.7 V - 3.6 V Note
W1 W2
tPHWL / tPHEL tELWL / tWLEL tWLWH / tELEH tDVWH / tDVEH tAVWH / tAVEH tWHEH / tEHWH tWHDX / tEHDX tWHAX / tEHAX tWHWL / tEHEL
RP# High Recovery to WE# (CE#) Going Low CE# (WE#) Setup to WE# (CE#) Going Low WE# (CE#) Pulse Width
4,5 4,5
150 0
150 0
150 0
150 0
150 0
150 0
ns ns
W3
1,4,5
45
60
60
70
70
70
ns
W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14
Data Setup to WE# (CE#) Going High Address Setup to WE# (CE#) Going High CE# (WE#) Hold Time from WE# (CE#) High Data Hold Time from WE# (CE#) High Address Hold Time from WE# (CE#) High WE# (CE#) Pulse Width High
2,4,5 2,4,5 4,5 2,4,5 2,4,5 1,4,5 3,4,5 3,4 3,4 3,4 3,4
40 50 0 0 0 25 200 0 0 0 30
40 60 0 0 0 30 200 0 0 0 30
50 60 0 0 0 30 200 0 0 0 30
60 70 0 0 0 30 200 0 0 0 30
60 70 0 0 0 30 200 0 0 0 30
60 70 0 0 0 30 200 0 0 0 30
ns ns ns ns ns ns ns ns ns ns ns
tVPWH / VPP Setup to WE# (CE#) Going High tVPEH tQVVL tBHWH / tBHEH tQVBL tWHGL VPP Hold from Valid SRD WP# Setup to WE# (CE#) Going High WP# Hold from Valid SRD WE# High to OE# Going Low
Notes: 1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). So tWP = tWLWH = tELEH = tWLEH = tELWH.
2. 3. 4. 5. 6.
Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). So tWPH = tWHWL = tEHEL = tWHEL = tEHWL. Refer to Table 27 "Bus Operations(1)" on page 51 for valid AIN or DIN. Sampled, but not 100% tested. See Figure 12 "AC Input/Output Reference Waveform" on page 46 for timing measurements and maximum allowable input slew rate. See Figure 11 "Write Operations Waveform" on page 45. VCCMax = 3.3 V for 32-Mbit 0.25 Micron product.
Datasheet
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
18 Aug 2005 43
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 22.
Write Operations--64-Mbit Density
Density 64 Mbit 80 ns Note Min Unit
#
Symbol
Parameter VCC
Product 2.7 V - 3.6 V
W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14
tPHWL / tPHEL tELWL / tWLEL tWLWH / tELEH tDVWH / tDVEH tAVWH / tAVEH tWHEH / tEHWH tWHDX / tEHDX tWHAX / tEHAX tWHWL / tEHEL tVPWH / tVPEH tQVVL tBHWH / tBHEH tQVBL tWHGL
RP# High Recovery to WE# (CE#) Going Low CE# (WE#) Setup to WE# (CE#) Going Low WE# (CE#) Pulse Width Data Setup to WE# (CE#) Going High Address Setup to WE# (CE#) Going High CE# (WE#) Hold Time from WE# (CE#) High Data Hold Time from WE# (CE#) High Address Hold Time from WE# (CE#) High WE# (CE#) Pulse Width High VPP Setup to WE# (CE#) Going High VPP Hold from Valid SRD WP# Setup to WE# (CE#) Going High WP# Hold from Valid SRD WE# High to OE# Going Low
4,5 4,5 1,4,5 2,4,5 2,4,5 4,5 2,4,5 2,4,5 1,4,5 3,4,5 3,4 3,4 3,4 3,4
150 0 60 40 60 0 0 0 30 200 0 0 0 30
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). So tWP = tWLWH = tELEH = tWLEH = tELWH.
2. 3. 4. 5.
Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). So tWPH = tWHWL = tEHEL = tWHEL = tEHWL. Refer to Table 27 "Bus Operations(1)" on page 51 for valid AIN or DIN. Sampled, but not 100% tested. See Figure 12 "AC Input/Output Reference Waveform" on page 46 for timing measurements and maximum allowable input slew rate. See Figure 11 "Write Operations Waveform" on page 45.
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Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
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Figure 11.
Write Operations Waveform
W5 Address [A]
W8
W6 CE# [E] W3 W2 WE# [W] OE# [G] W4 Data [D/Q] W1 RP# [P] W10 Vpp [V] W7 W9
8.3
Table 23.
Erase and Program Timing
Erase and Program Timing
VPP Symbol Parameter Note Typ Max Typ Max 1.65 V-3.6 V 11.4 V-12.6 V Unit
tBWPB tBWMB
4-KW Parameter Block Word Program Time 32-KW Main Block Word Program Time Word Program Time for 0.13 and 0.18 Micron Product
1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1,3 1,3
0.10 0.8 12 22 0.5 1 5 5
0.30 2.4 200 200 4 5 10 20
0.03 0.24 8 8 0.4 0.6 5 5
0.12 1 185 185 4 5 10 20
s s s s s s s s
tWHQV1 / tEHQV1
Word Program Time for 0.25 Micron Product 4-KW Parameter Block Erase Time 32-KW Main Block Erase Time Program Suspend Latency Erase Suspend Latency
tWHQV2 / tEHQV2 tWHQV3 / tEHQV3 tWHRH1 / tEHRH1 tWHRH2 / tEHRH2
Notes: 1. Typical values measured at TA= +25 C and nominal voltages. 2. Excludes external system-level overhead. 3. Sampled, but not 100% tested.
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
8.4
Figure 12.
AC I/O Test Conditions
AC Input/Output Reference Waveform
VCCQ Input 0V
Note:
VCCQ/2
Test Points
VCCQ/2
Output
Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst-case speed conditions are when VCC = VCCMin.
Figure 13.
Transient Equivalent Testing Load Circuit
VCCQ R1
Device Under Test
Out CL R2
Note:
See Table 24 for component values.
Table 24.
Test Configuration Component Values for Worst Case Speed Conditions
Test Configuration C L (pF) R1 (k) R2 (k)
VCCQMin Standard Test
Note:
50
25
25
CL includes jig capacitance.
8.5
Device Capacitance
TA = 25 C, f = 1 MHz
Table 25.
Device Capacitance
Symbol Parameter Typ Max Unit Condition
CIN COUT
Input Capacitance Output Capacitance
6 8
8 12
pF pF
VIN = 0.0 V VOUT = 0.0 V
Sampled, not 100% tested.
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9.0
9.1
Power and Reset Specifications
Power-Up/Down Characteristics
To prevent any condition that might result in a spurious write or erase operation, power-up VCC and V CCQ together. Conversely, V CC and VCCQ must power-down together. Also power-up VPP with or slightly after VCC. Conversely, VPP must power-down with or slightly before VCC. If VCCQ and/or VPP are not connected to the VCC supply, then VCC must attain V CCMin before applying VCCQ and VPP. Device inputs must not be driven before supply voltage = VCCMin. Power supply transitions must occur only when RP# is low.
9.1.1
RP# Connected to System Reset
Use RP# during system reset with automated program/erase devices, because the system expects to read from the flash memory when the system exits reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization does not occur, because the flash memory might be providing status information instead of array data. Connecting RP# to the system CPU RESET# signal to allow proper CPU/flash initialization after a system reset. System designers must guard against spurious writes when VCC voltages are above VLKO. Because both WE# and CE# must be low for a command write, driving either signal to VIH inhibits writes to the flash memory device. The CUI architecture provides additional protection, because memory contents can be altered only after successful completion of the two-step command sequences. The flash memory device is also disabled until RP# is brought to V IH, regardless of the state of its control inputs. By holding the device in reset (RP# connected to system POWERGOOD) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection.
9.1.2
VCC, VPP, and RP# Transitions
The CUI latches commands as issued by system software, and is not altered by V PP or CE# transitions or WSM actions. The CUI default state upon power-up, after exit from reset mode or after VCC transitions above V LKO (Lockout voltage), is read-array mode. After any program or Block-Erase operation is complete (even after VPP transitions down to VPPLK), the CUI must be reset to read-array mode, using the Read Array command if access to the flash-memory array is required.
Datasheet
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
18 Aug 2005 47
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
9.2
Table 26.
Reset Specifications
Reset Specifications
VCC 2.7 V - 3.6 V Symbol Parameter Min Max Unit Notes
tPLPH tPLRH1 tPLRH2
RP# Low to Reset during Read (If RP# is tied to VCC, this specification is not applicable) RP# Low to Reset during Block Erase RP# Low to Reset during Program
100 22 12
ns s s
1, 2 3 3
Notes: 1. If tPLPH is < 100 ns, the device can still reset, but reset is not guaranteed. 2. If RP# is asserted while a Block Erase or Word Program operation is not executing, the reset completes within 100 ns. 3. Sampled, but not 100% tested.
Figure 14.
Deep Power-Down/Reset Operations Waveforms
RP# (P)
VIH VIL
t PLPH (A) Reset during Read Mode
t PHQV t PHWL t PHEL
t PLRH
RP# (P)
Abort Complete
VIH V IL
t PHQV t PHWL t PHEL
t PLPH (B) Reset during Program or Block Erase, t PLPH < t PLRH
Abort Deep Complete PowerDown
RP# (P)
VIH V IL
t PLRH
t PHQV t PHWL t PHEL
t PLPH
(C) Reset Program or Block Erase, t PLPH > t PLRH
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9.3
Power Supply Decoupling
Flash memory power-switching characteristics require careful device decoupling. System designers must consider the following three supply current issues: 1. Standby current levels (ICCS). 2. Read current levels (ICCR). 3. Transient peaks produced by falling and rising edges of CE#. Transient current magnitudes depend on the device output capacitive and inductive loading. Two-line control and proper decoupling capacitor selection suppresses these transient voltage peaks. Each flash device must have a 0.1 F ceramic capacitor connected between each V CC and GND, and between its VPP and GND. These high-frequency, inherently low-inductance capacitors must be placed as close as possible to the package leads.
9.4
Power Consumption
Intel(R) flash memory devices use a tiered approach to power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the flash memory device is selected but idle. If CE# is deasserted, the flash memory device enters its standby mode, where current consumption is even lower. The combination of these features can minimize memory power consumption, and therefore minimize overall system power consumption.
9.4.1
Active Power
When CE# is at a logic-low level and RP# is at a logic-high level, the flash memory device is in the active mode. Refer to the DC Characteristic tables for ICC current values. Active power is the largest contributor to overall system power consumption. Minimizing the active current can profoundly affect system power consumption, especially for battery-operated devices.
9.4.2
Automatic Power Savings (APS)
Automatic Power Savings provides low-power operation during read mode. After data is read from the flash memory array and the address lines are quiescent, APS circuitry places the flash memory device in a mode where typical current is comparable to ICCS. The flash memory stays in this static state with outputs valid until a new location is read.
9.4.3
Standby Power
When CE# is at a logic-high level (VIH) and the flash memory device is in read mode, the flash memory is in standby mode. This mode disables much of the device circuitry, and substantially reduces power consumption. Outputs are placed in a high-impedance state independent of the status of the OE# signal. If CE# transitions to a logic-high level during Erase or Program operations, the flash memory device continues to perform the operation and consume corresponding active power until the operation is completed. System engineers must analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. This approach provides a more accurate measure of application-specific power and energy requirements. Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
Datasheet
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
9.4.4
Deep Power-Down Mode
The deep power-down mode is activated when RP# = VIL (GND 0.2 V). During read modes, RP# going low deselects the flash memory and places the outputs in a high-impedance state. Recovery from deep power-down mode requires a minimum time of tPHQV (see "AC Read Characteristics" on page 37). During program or erase modes, RP# transitioning low aborts the in-progress operation. The memory contents of the address being programmed or the block being erased are no longer valid, because the abort compromises data integrity. During deep power-down, all internal circuits switch to a low-power savings mode (RP# transitioning to V IL or turning off power to the flash memory device clears the Status Register).
10.0
Operations Overview
Flash memory combines EEPROM functionality with in-circuit electrical program-and-erase capability. The B3 flash memory device family uses a Command User Interface (CUI) and automated algorithms to simplify Program and Erase operations. The CUI allows for 100% CMOS-level control inputs and fixed power supplies during erasure and programming. When V PP < VPPLK, the flash memory device executes only the following commands successfully:
* * * *
Read Array Read Status Register Clear Status Register Read Identifier
The flash memory device provides standard EEPROM read, standby, and Output-Disable operations. Manufacturer identification and device identification data can be accessed through the CUI. All functions that alter memory contents (program and erase) are accessible through the CUI. The internal Write State Machine (WSM) completely automates Program and Erase operations, while the CUI signals the start of an operation and the Status Register reports status. The CUI handles the WE# interface to the data and address latches, and system status requests during WSM operation.
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Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
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10.1
Bus Operations
The B3 flash memory device performs read, program, and erase in-system operations through the local CPU or microcontroller. All bus cycles to or from the flash memory conform to standard microcontroller bus cycles. Four control pins dictate the data flow in and out of the flash memory device:
* * * *
CE# OE# WE# RP#
Table 27 summarizes these bus operations. Table 27. Bus Operations(1)
Mode Note RP# CE# OE# WE# DQ0-7 DQ8-15
Read (Array, Status, or Identifier) Output Disable Standby Reset Write
2-4 2 2 2, 7 2, 5-7
VIH VIH VIH VIL VIH
VIL VIL VIH X VIL
VIL VIH X X VIH
VIH VIH X X VIL
DOUT High Z High Z High Z DIN
DOUT High Z High Z High Z DIN
Notes: 1. 8-bit devices use only DQ[0:7]. 16-bit devices use DQ[0:15]. 2. X must be VIL, VIH for control pins and addresses. 3. See DC Characteristics for VPPLK, VPP1, VPP2, VPP3, VPP4 voltages. 4. Manufacturer and device codes can also be accessed in read identifier mode (A1-A21 = 0). See Table 29. 5. Refer to Table 30 for valid DIN during a Write operation. 6. To program or erase the lockable blocks, hold WP# at VIH. 7. RP# must be at GND 0.2 V to meet the maximum deep power-down current specified.
10.1.1
Read
The B3 flash memory device provides four read modes:
* * * *
read array read identifier read status read query
These modes are accessible independently of the VPP voltage. Issue the appropriate Read Mode command to the CUI to enter the corresponding mode. Upon initial device power-up or after exit from reset, the flash memory device automatically defaults to read-array mode. CE# and OE# must be driven active to obtain data at the outputs.
* CE# is the device selection control. When active, CE# enables the flash memory device. * OE# is the data output control, and drives the selected memory data onto the I/O bus.
For all read modes, WE# and RP# must be at VIH. Figure 10 on page 40 illustrates a read cycle. Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 51
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10.1.2
Output Disable
When OE# is at a logic-high level (VIH), the flash memory device outputs are disabled. Output pins are placed in a high-impedance state.
10.1.3
Standby
Deselecting the flash memory device by bringing CE# to a logic-high level (VIH) places the device in standby mode. Standby mode substantially reduces device power consumption, without any latency for subsequent read accesses. In standby mode, outputs are placed in a high-impedance state independent of OE#. If deselected during Program or Erase operation, the flash memory device continues to consume active power until the Program or Erase operation is complete.
10.1.4
Deep Power-Down / Reset
From read mode, RP# at V IL for time tPLPH does the following:
* * * * *
Deselects the flash memory. Places output drivers in a high-impedance state. Turns off all internal circuits. After a return from reset, a time tPHQV is required until the initial read-access outputs are valid. After a return from reset, a delay (tPHWL or tPHEL) is required before a write can be initiated.
After this wake-up interval, normal operation is restored. The CUI resets to read-array mode, and the Status Register is set to 80H. Figure 14 "Deep Power-Down/Reset Operations Waveforms" on page 48 (A) illustrates this case. If RP# is taken low for time tPLPH during a Program or Erase operation, the operation aborts. The memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, because the data might be partially erased or written. The abort process uses the following sequence: 1. When RP# goes low, the flash memory device shuts down the operation in progress, a process that takes time tPLRH to complete. 2. After this time tPLRH, the flash memory device either resets to read-array mode (if RP# has gone high during tPLRH, see Figure 14 "Deep Power-Down/Reset Operations Waveforms" on page 48 (B)), or enters reset mode (if RP# is still logic low after tPLRH, see Figure 14 "Deep Power-Down/Reset Operations Waveforms" on page 48 (C)). 3. In both cases, after returning from an aborted operation, the relevant time tPHQV or tPHWL/ tPHEL must elapse before initiating a Read or Write operation, as discussed in the previous paragraph. However, in this case, these delays are referenced to the end of tPLRH rather than when RP# goes high. As with any automated device, RP# must be asserted during system reset. When the system finishes reset, the processor expects to read from the flash memory. Automated flash memories provide status information when read during program or Block-Erase operations. If a CPU reset occurs with no flash memory reset, proper CPU initialization cannot occur, because the flash memory might be providing status information instead of array data. Intel(R) Flash memories allow proper CPU initialization after a system reset, using the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. 18 Aug 2005 52 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet
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10.1.5
Write
A write occurs when both CE# and WE# are low and OE# is high. Commands are written to the Command User Interface (CUI) using standard microprocessor write timings to control flash memory operations. The CUI does not occupy an addressable memory location. The address and data buses are latched on the rising edge of the second WE# or CE# pulse, whichever occurs first. Table 30 shows the available commands, and Appendix A provides detailed information about moving between the different modes of operation using CUI commands. Two commands modify array data:
* Program (40H). * Erase (20H).
Writing either of these commands to the internal Command User Interface (CUI) initiates a sequence of internally timed functions that culminate in the completion of the requested task (unless that operation is aborted by either RP# being driven to V IL for tPLRH or an appropriate Suspend command).
11.0
Operating Modes
The flash memory device has four read modes:
* * * *
read array read identifier read status read query
See Figure 1 "B3 Architecture Block Diagram" on page 10). The flash memory device also has two write modes:
* program * block erase
Three additional modes are available only during suspended operations:
* erase suspend to program * erase suspend to read * program suspend to read
Table 28 "Command Codes and Descriptions" on page 54 summarizes the commands used to reach these modes. Appendix A, "Write State Machine Current/Next States," is a comprehensive chart showing the state transitions.
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11.1
Read Array
When RP# transitions from VIL (reset) to VIH, the flash memory device defaults to read-array mode and responds to the read-control inputs (CE#, address inputs, and OE#) without any additional CUI commands. When the flash memory device is in read-array mode, four control signals control data output:
* * * *
WE# must be logic high (VIH) CE# must be logic low (VIL) OE# must be logic low (VIL) RP# must be logic high (VIH)
In addition, the address of the preferred location must be applied to the address pins. If the flash memory device is not in read-array mode, such as after a Program or Erase operation, the Read Array command (FFH) must be written to the CUI before array reads can occur. Table 28.
Code
Command Codes and Descriptions (Sheet 1 of 2)
Device Mode Description
00, 01, 60, 2F, C0, 98 FF
Invalid/ Reserved Read Array
Unassigned commands that must not be used. Intel reserves the right to redefine these codes for future functions. Places the flash memory device in read-array mode, so that array data is output on the data pins. A two-cycle command. * The first cycle prepares the CUI for a program operation. * The second cycle latches addresses and data information, and initiates the WSM to execute the program algorithm. The flash memory device outputs Status Register data when CE# or OE# is toggled. To read array data, a Read Array command is required after programming. See Section 11.4. (See 40H/Program Set-Up) Prepares the CUI for the Erase Confirm command. If the next command is not an Erase Confirm command, then the CUI does the following: 1. Sets both SR.4 and SR.5 of the Status Register to 1. 2. Places the flash memory device into the read-Status Register mode. 3. Waits for another command. See Section 11.5, "Erase Mode" on page 58. If the previous command was an Erase Set-Up command, then the CUI closes the address and data latches, and begins erasing the block indicated on the address pins. During erase, the flash memory device responds only to the Read Status Register and Erase Suspend commands. The device outputs Status Register data when CE# or OE# is toggled. If a Program or Erase operation was previously suspended, this command resumes that operation.
40
Program Set-Up
10
Alternate Program Set-Up
20
Erase Set-Up
Erase Confirm D0 Program / Erase Resume
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Table 28.
Code
Command Codes and Descriptions (Sheet 2 of 2)
Device Mode Description
B0
Program / Erase Suspend
Issuing this command suspends the currently executing Program/Erase operation. To indicate when the operation has been successfully suspended, the Status Register sets either the program suspend (SR.2) or erase suspend (SR.6), and sets the WSM status bit (SR.7) to 1 (ready). The WSM continues to idle in the SUSPEND state, regardless of the state of all input-control pins except RP#, which immediately shuts down the WSM and the remainder of the device, if it is driven to VIL. See Section 11.4.1, "Suspending and Resuming Programming" on page 58 and Section 11.4.1, "Suspending and Resuming Programming" on page 58. This command places the flash memory device into Read-Status Register mode. Reading the device outputs the contents of the Status Register, regardless of the address presented to the device. The flash memory device automatically enters this mode after a Program or Erase operation is initiated. See Section 11.3, "Read Status Register" on page 56. The WSM can set the block-lock status (SR.1), VPP status (SR.3), program status (SR.4), and erase status (SR.5) bits in the Status Register to 1. However, the WSM cannot clear these bits to 0. Issuing this command clears these bits to 0. Places the flash memory device into the intelligent-identifier-read mode, so that reading the device outputs the manufacturer and device codes (A0 = 0 for manufacturer, A0 = 1 for the device; all other address inputs must be 0). See Section 11.2, "Read Identifier" on page 56.
70
Read Status Register
50
Clear Status Register
90
Read Identifier
Note:
See Chapter 14.0, "Write State Machine Current/Next States," for mode transition information.
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11.2
Read Identifier
To read the manufacturer and device codes, the flash memory device must be in read-identifier mode, which can be reached by writing the Read Identifier command (90H). As shown in Table 29, once in read-identifier mode:
* A0 = 0 outputs the manufacturer identification code. * A0 = 1 outputs the device identifier.
Note: A1-A21 = 0. To return to read-array mode, write the Read-Array command (FFH). Table 29. Read Identifier Table
Device Identifier Size Mfr. ID -T (Top Boot) -B (Bottom Boot)
28F004B3 0089H 28F400B3 28F008B3 28F800B3 28F016B3 28F160B3 28F320B3 28F640B3 0089H 0089H
D4H 8894H D2H 8892H D0H 8890H 8896H 8898H
D5H 8895H D3H 8893H D1H 8891H 8897H 8899H
11.3
Read Status Register
The flash memory device Status Register indicates when a Program or Erase operation is complete, and the success or failure of that operation.
* To read the Status Register, issue the Read Status Register (70H) command to the CUI.
This command causes all subsequent Read operations to output data from the Status Register until another command is written to the CUI.
* To return to reading from the array, issue the Read Array (FFH) command.
The Status Register bits are output on DQ0-DQ7. The upper byte, DQ8-DQ15, outputs 00H during a Read Status Register command. The contents of the Status Register are latched on the falling edge of OE# or CE#, which prevents possible Bus errors that might occur if Status Register contents change while being read. CE# or OE# must be toggled with each subsequent status read, or the Status Register does not indicate completion of a Program or Erase operation. When the WSM is active, SR.7 indicates the status of the WSM. The remaining bits in the Status Register indicate whether the WSM was successful in performing the preferred operation (see Table 31 on page 60).
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11.3.1
Clearing the Status Register
The WSM sets status bits 1 through 7 to 1, and clears bits 2, 6, and 7 to 0. However, the WSM cannot clear status bits 1 or 3 through 5 to 0. Because bits 1, 3, 4, and 5 indicate various error conditions, these bits can be cleared only through the Clear Status Register (50H) command. By allowing the system software to control the resetting of these bits, several operations can be performed (such as cumulatively programming several addresses or erasing multiple blocks in sequence) before reading the Status Register to determine if an error occurred during that series. Clear the Status Register before beginning another command or sequence.
Note:
The Read Array command must be issued before data can be read from the flash memory array.
11.4
Program Mode
Programming is executed using a two-write sequence. 1. The Program Setup command (40H) is written to the CUI. 2. A second write specifies the address and data to program. The WSM executes a sequence of internally timed events to program preferred bits of the addressed location. The WSM then verifies that the bits are sufficiently programmed. Programming the memory changes specific bits within an address location to 0. If users attempt to program 1 instead of 0, the memory cell contents do not change and no error occurs. The Status Register indicates the programming status: while the program sequence executes, status bit 7 is 0. To poll the Status Register, toggle either CE# or OE#. While programming, the only valid commands are:
* Read Status Register * Program Suspend * Program Resume
When programming is complete, the program-status bits must be checked.
* If the programming operation was unsuccessful, SR.4 is set, indicating a program failure. * If SR.3 is set, then VPP was not within acceptable limits, and the WSM did not execute the
program command.
* If SR.1 is set, a program operation was attempted on a locked block and the operation aborted.
Clear the Status Register before attempting the next operation. Any CUI instruction can follow after programming is completed; however, to prevent inadvertent Status Register reads, be sure to reset the CUI to read-array mode.
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11.4.1
Suspending and Resuming Programming
The Program Suspend command halts the in-progress program operation to read data from another flash memory location. 1. After the programming process starts, writing the Program Suspend command to the CUI requests that the WSM suspend the program sequence (at predetermined points in the program algorithm). 2. The flash memory device continues to output Status Register data after the Program Suspend command is written. 3. Polling SR.7 and SR.2 determines when the program operation has been suspended (both are set to 1). tWHRH1/tEHRH1 specifies the program- suspend latency. 4. A Read Array command can now be written to the CUI to read data from blocks other than the suspended block. The only other valid commands while program is suspended are: -- Read Status Register -- Read Identifier -- Program Resume 5. After the Program Resume command is written to the flash memory, the WSM continues with the program process, and Status Register bits SR.2 and SR.7 are automatically cleared. 6. After the Program Resume command is written, the flash memory device automatically outputs Status Register data when read. See Appendix B, "Program and Erase Flowcharts."
Note:
VPP must remain at the same V PP level used for program while in program-suspend mode. RP# must also remain at VIH.
11.5
Erase Mode
To erase a block: 1. Write the Erase Set-up and Erase Confirm commands to the CUI, along with an address identifying the block to be erased. This address is latched internally when the Erase Confirm command is issued. Block erasure sets all bits within the block to 1. Only one block can be erased at a time. 2. The WSM executes a sequence of internally timed events : a. programs all bits within the block to 0. b. Erases all bits within the block to 1. c. Verifies that all bits within the block are sufficiently erased. While the erase executes, status bit 7 is 0.
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3. When the Status Register indicates that erasure is complete, check the erase-status bit to verify that the Erase operation was successful. -- If the Erase operation was unsuccessful, SR.5 of the Status Register is set to 1, indicating an erase failure. -- If VPP was not within acceptable limits after the Erase Confirm command was issued, the WSM does not execute the erase sequence. Instead, SR.5 is set to indicate an Erase error, and SR.3 is set to 1, indicating that the VPP supply voltage was not within acceptable limits. 4. After an Erase operation, clear the Status Register (50H) before attempting the next operation. Any CUI instruction can follow after erasure is completed. 5. To prevent inadvertent status- register reads, place the flash memory device in read-array mode after the erase is complete.
11.5.1
Suspending and Resuming Erase
Because an Erase operation requires on the order of seconds to complete, an Erase Suspend command is provided. Erase Suspend interrupts an erase sequence to read data from--or program data to-- another block in memory. After the erase sequence is started, writing the Erase Suspend command to the CUI requests that the WSM pauses the erase sequence at a predetermined point in the erase algorithm.
Note:
The Status Register will indicates if/when the Erase operation has been suspended.
* A Read Array/Program command can now be written to the CUI, to read data from/ program
data to blocks other than the one currently suspended.
* The Program command can subsequently be suspended to read yet another array location.
The only valid commands while Erase is suspended are:
* * * * *
Erase Resume Program Read Array Read Status Register Read Identifier
During erase-suspend mode, to place the flash memory device in a pseudo-standby mode, set CE# to VIH, which reduces active current consumption. Erase Resume continues the erase sequence when CE# = VIL. As with the end of a standard Erase operation, the Status Register must be read and cleared before the next instruction is issued.
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Table 30.
Command Bus Definitions
(1,4)
First Bus Cycle Command Notes Oper Addr Data
Second Bus Cycle Oper Addr Data
Read Array Read Identifier Read Status Register Clear Status Register Program Block Erase/Confirm Program/Erase Suspend Program/Erase Resume
Notes:
PA: Program Address IA: Identifier Address
Write 2 Write Write Write 3 Write Write Write Write
X X X X X X X X
FFH 90H 70H 50H 40H / 10H 20H B0H D0H Write Write PA BA PD D0H Read Read IA X ID SRD
PD: Program Data ID: Identifier Data
BA: Block Address SRD: Status Register Data
1. 2.
3. 4.
Bus operations are defined in Table 27. Following the Intelligent Identifier command, two Read operations access manufacturer and device codes. - A 0 = 0 for manufacturer code. - A0 = 1 for device code. - A1-A21 = 0. Either the 40H or 10H command is valid. The standard is 40H. When writing commands to the flash memory device, the upper data bus [DQ 8-DQ15] must be either VIL or VIH, to minimize current draw.
Table 31.
WSMS 7
Status Register Bit Definition
ESS 6 ES 5 PS 4 VPPS 3 PSS 2 BLS 1 R 0
Bits
NOTES:
SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = ERASE-SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase In Progress/Completed SR.5 = ERASE STATUS (ES) 1 = Error In Block Erasure 0 = Successful Block Erase SR.4 = PROGRAM STATUS (PS) 1 = Error in Word Program 0 = Successful Word Program
Check Write State Machine bit first to determine word program or block-erase completion, before checking program or erasestatus bits. When erase suspend is issued, WSM halts execution and sets both WSMS and ESS bits to 1. ESS bit remains set at 1 until an Erase Resume command is issued. When this bit is set to 1, WSM has applied the maximum number of erase pulses to the block and is still unable to verify successful block erasure. When this bit is set to 1, WSM has attempted but failed to program a word.
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Bits
NOTES:
SR.3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK
The VPP status bit does not continuously indicate the VPP level. The WSM interrogates the VPP level only after the Program or Erase command sequences are entered, and informs the system if VPP has not been switched on. The VPP is also checked before the WSM verifies the operation. The VPP status bit is not guaranteed to report accurate feedback between VPPLK max and VPP1 min or between VPP1 max and VPP4 min. When program suspend is issued, WSM halts execution and sets both WSMS and PSS bits to 1. The PSS bit remains set to 1 until a Program Resume command is issued. If a Program or Erase operation is attempted to one of the locked blocks, the WSM sets this bit. The operation specified is aborted and the flash memory device returns to read status mode. This bit is reserved for future use and must be masked out when polling the Status Register.
SR.2 = PROGRAM SUSPEND STATUS (PSS) 1 = Program Suspended 0 = Program in Progress/Completed SR.1 = BLOCK LOCK STATUS 1 = Program/Erase attempted on locked block; Operation aborted 0 = No operation to locked blocks SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Note:
A Command Sequence Error is indicated when SR.4, SR.5, and SR.7 are set.
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12.0
Block Locking
The B3 flash memory device architecture features two hardware-lockable parameter blocks.
12.1
WP# = VIL for Block Locking
The lockable blocks are locked when WP# = V IL; any program or Erase operation to a locked block results in an error, which is reflected in the Status Register:
* For top configuration, the top two parameter blocks are lockable:
-- blocks #133 and #134 for 64 Mbit -- blocks #69 and #70 for 32 Mbit -- blocks #37 and #38 for 16 Mbit -- blocks #21 and #22 for 8 Mbit -- blocks #13 and #14 for 4 Mbit
* For the bottom configuration, the bottom two parameter blocks are lockable. These are blocks
#0 and #1 for 4, 8 , 16, 32, and 64 Mbit. Unlocked blocks can be programmed or erased normally (unless V PP is below VPPLK).
12.2
WP# = VIH for Block Unlocking
WP# = VIH unlocks all lockable blocks. These blocks can now be programmed or erased.
Note:
RP# does not override WP# locking for the B3 flash memory device, as in previous Boot Block devices.
* WP# controls all block locking. * VPP provides protection against spurious writes.
Table 32 defines the write- protection methods. Table 32. Write-Protection Truth Table for the B3 Device Family
VPP WP# RP# Write Protection Provided
X VIL
VPPLK VPPLK
X X VIL VIH
VIL VIH VIH VIH
All Blocks Locked All Blocks Locked Lockable Blocks Locked All Blocks Unlocked
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13.0
VPP Program and Erase Voltages
TheB3 flash memory device products provide in-system programming and erase at 2.7 V. For customers requiring fast programming in their manufacturing environment, the B3 flash memory device includes an additional low-cost 12-V programming feature. The 12-V VPP mode enhances programming performance during the short period of time typically found in manufacturing processes. However, this mode is not intended for extended use. 12 V can be applied to V PP during program and Erase operations for a maximum of 1000 cycles on the main blocks, and 2500 cycles on the parameter blocks. VPP can be connected to 12 V for a total of 80 hours maximum.
Warning:
Stressing the flash memory device beyond these limits might cause permanent damage. During Read operations or idle times, V PP can be tied to a 5-V supply. For Program and Erase operations, a 5-V supply is not permitted. The V PP must be supplied with either 2.7 V to 3.6 V or 11.4 V to 12.6 V during Program and Erase operations.
13.1
VPP = VIL for Complete Protection
The VPP programming voltage can be held low for complete write protection of all blocks in the flash memory device. When VPP is below VPPLK, any Program or Erase operation results in an error, prompting the corresponding SR.3 to be set.
14.0
Additional Information
Order Number
Document/Tool Intel Advanced Boot Block Flash Memory Family Specification Update AP-641 Achieving Low Power with the 3 Volt Advanced Boot Block Flash Memory AP-642 Designing for Upgrade to the 3 Volt Advanced Boot Block Flash Memory 3 Volt Advanced Boot Block Algorithms (`C' and assembly)
297948 292199 292200 Note 2
http://developer.intel.com/design/flash/swtools Contact your Intel Representative 297874
Intel(R) Flash Data Integrator (IFDI) Software Developer's Kit IFDI Interactive: Play with Intel(R) Flash Data Integrator on Your PC
Notes: 1. Call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers must contact their local Intel or distribution sales office. 2. Visit the Intel home page at http://www.Intel.com or http://developer.intel.com for technical documentation and tools. 3. For the most current information about Intel Advanced Boot Block Flash memory and Intel Advanced+ Boot Block Flash memory, visit http://developer.intel.com/design/flash/
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(R)
(R)
(R)
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Appendix A Write State Machine Current/Next States
Table 33. Write State Machine (Sheet 1 of 2)
Command Input (and Next State) Current State Data When Read Read Array (FFH) Program Setup (10/40H) Erase Setup (20H) Erase Confirm (D0H) Prog/Ers Suspend (B0H) Prog/Ers Resume (D0H) Read Status (70H) Clear Status (50H) Read Identifier. (90H)
SR.7
Read Array Read Status Read Identifier Prog. Setup Program (continue)
"1" "1" "1" "1"
Array Status Identifier Status
Read Array Read Array Read Array
Program Setup Program Setup Program Setup
Erase Setup Erase Setup Erase Setup
Read Array Read Array Read Array
Read Status Read Status Read Status
Read Array Read Array Read Array
Read Identifier Read Identifier Read Identifier
Program (Command Input = Data to be Programmed) Prog. Sysop. to Rd. Status Program (continue ) Program Susp. to Read Array Program Susp. to Read Array Program Susp. to Read Array Read Array Erase (continue ) Erase Cant. Error Read Array Erase Sus. to Read Status Erase (continue ) Program (continue )
"0"
Status
Program (continue)
Program (continue)
Program Suspend to Read Status
"1"
Status
Prog. Susp. to Read Array Prog. Susp. to Read Array Prog. Susp. to Read Array Read Array
Program Suspend to Read Array
Prog. Susp. to Read Status Prog. Susp. to Read Status Prog. Susp. to Read Status Read Status
Prog. Susp. to Read Array Prog. Sus. to Read Array Prog. Sus. to Read Array Read Array
Prog. Susp. to Read Identifier Prog. Susp. to Read Identifier Prog. Susp. to Read Identifier Read Identifier
Program Suspend to Read Array
"1"
Array
Program Suspend to Read Array
Program (continue )
Program (continue )
Prog. Susp. to Read Identifier Program (complete) Erase Setup Erase Cant. Error Erase (continue)
"1"
Identifier
Program Suspend to Read Array
Program (continue )
Program (continue )
"1"
Status
Program Setup
Erase Setup
"1"
Status
Erase Command Error Read Array Program Setup Erase Setup
Erase Command Error Read Status Read Array Read Identifier
"1"
Status
"0"
Status
Erase (continue)
Erase (continue)
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Table 33.
Write State Machine (Sheet 2 of 2)
Command Input (and Next State)
Current State
SR.7
Data When Read
Read Array (FFH)
Program Setup (10/40H)
Erase Setup (20H)
Erase Confirm (D0H)
Prog/Ers Suspend (B0H)
Prog/Ers Resume (D0H)
Read Status (70H)
Clear Status (50H)
Read Identifier. (90H)
Erase Suspend to Status
"1"
Status
Erase Susp. to Read Array Erase Susp. to Read Array Erase Susp. to Read Array Read Array
Program Setup
Erase Susp. to Read Array Erase Susp. to Read Array Erase Susp. to Read Array Erase Setup
Erase
Erase Susp. to Read Array Erase Susp. to Read Array Erase Susp. to Read Array Read Array
Erase
Erase Susp. to Read Status Erase Susp. to Read Status Erase Susp. to Read Status Read Status
Erase Susp. to Read Array Erase Susp. to Read Array Erase Susp. to Read Array Read Array
Ers. Susp. to Read Identifier Ers. Susp. to Read Identifier Ers. Susp. to Read Identifier Read Identifier
Erase Susp. to Read Array
"1"
Array
Program Setup
Erase
Erase
Erase Susp. to Read Identifier Erase (complete)
"1"
Identifier
Program Setup
Erase
Erase
"1"
Status
Program Setup
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Appendix B Program and Erase Flowcharts
Figure 15. Program Flowchart
Start
Bus Operation Write Write Command Program Setup Program Comments Data = 40H Data = Data to Program Addr = Location to Program Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 40H
Program Address/Data
Read
Read Status Register
Standby
SR.7 = 1? Yes Full Status Check if Desired
No
Repeat for subsequent programming operations. SR Full Status Check can be done after each program or after a sequence of program operations. Write FFH after the last program operation to reset device to read array mode.
Program Complete
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.4 = 0 1 SR.1 = 0 Program Successful
If an error is detected, clear the status register before attempting retry or other error recovery.
Bus Operation Standby
Command
Comments Check SR.3 1 = VPP Low Detect Check SR.4 1 = VPP Program Error Check SR.1 1 = Attempted Program to Locked Block - Program Aborted
VPP Range Error 1 Programming Error
Standby
Standby
SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine.
Attempted Program to Locked Block - Aborted
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are programmed before full status is checked.
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 16.
Program Suspend/Resume Flowchart
Bus Operation Write
Start
Command Program Suspend Read Status
Comments Data = B0H Addr = X Data = 70H Addr = X Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.2 1 = Program Suspended 0 = Program Completed
Write B0H
Write
Write 70H
Read
Read Status Register
Standby
SR.7 = 1 SR.2 = 1 Write FFH
0
Standby
Write
Read Array
0
Data = FFH Addr = X Read array data from block other than the one being programmed.
Program Completed
Read Program Resume
Write
Data = D0H Addr = X
Read Array Data
Done Reading Yes Write D0H
No
Write FFH
Program Resumed
Read Array Data
Datasheet
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
18 Aug 2005 67
www..com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 17.
Block Erase Flowchart
Start
Bus Operation Command Comments Data = 20H Addr = Within Block to Be Erased Data = D0H Addr = Within Block to Be Erased Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 20H
Write
Erase Setup
Write D0H and Block Address
Write
Erase Confirm
Read
Read Status Register No
Suspend Erase Loop 0 Suspend Erase Yes
Standby
SR.7 = 1 Full Status Check if Desired
Repeat for subsequent block erasures. Full Status Check can be done after each block erase or after a sequence of block erasures. Write FFH after the last write operation to reset device to read array mode.
Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.4,5 = 0 1 SR.5 = 0 1 SR.1 = 0 Block Erase Successful Attempted Erase of Locked Block - Aborted
SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are erased before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. Bus Operation Standby Command Comments Check SR.3 1 = V PP Low Detect Check SR.4,5 Both 1 = Command Sequence Error Check SR.5 1 = Block Erase Error Check SR.1 1 = Attempted Erase of Locked Block - Erase Aborted
VPP Range Error
Standby
1
Command Sequence Error
Standby
Standby
Block Erase Error
SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machine.
18 Aug 2005 68
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
Datasheet
www..com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 18.
Erase Suspend/Resume Flowchart
Start
Bus Operation Write
Command Erase Suspend Read Status
Comments Data = B0H Addr = X Data = 70H Addr = X Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.6 1 = Erase Suspended 0 = Erase Completed
Write B0H
Write
Write 70H
Read
Read Status Register
Standby
SR.7 = 1 SR.6 = 1 Write FFH
0
Standby
Write
Read Array
0
Data = FFH Addr = X Read array data from block other than the one being erased.
Erase Completed
Read
Write
Erase Resume
Data = D0H Addr = X
Read Array Data
Done Reading Yes Write D0H
No
Write FFH
Erase Resumed
Read Array Data
Datasheet
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
18 Aug 2005 69
www..com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Appendix C Ordering Information
Figure 19. Ordering Information
T E2 8 F 3 2 0 B3 T C7 0
Package TE = 48- Lead TSOP GT = 48- Ball BGA * CSP GE = VF BGA CSP RC = Easy BGA PC = Pb Free Easy BGA PH = Pb Free VFBGA JS = Pb Free TSOP Product line designator (R) for all Intel Flash products Device Density 640 = x16 (64 Mbit ) 320 = x16 (32 Mbit ) 160 = x16 (16 Mbit ) 800 = x16 (8 Mbit ) Access Speed (ns ) (70, 80 , 90, 100 , 110 ) Lithography A = 0.25 m C = 0.18 m D = 0.13 m T = Top Blocking B = Bottom Blocking
Product Family C3 = 3 Volt Advanced Boot B VCC = 2.7 V-3.6 V VPP = 2 .7 V-3 .6 V or 11 V-12 .6 V .4
Table 34.
Ordering Information: Valid Combinations (Sheet 1 of 2)
40-Lead TSOP 48-Lead TSOP 48-Ball BGA CSP(1,2) 48-Ball VF BGA
Ext. Temp. 64 Mbit
TE28F640B3TC80 TE28F640B3BC80 TE28F320B3TD70 TE28F320B3BD70 TE28F320B3TC70 TE28F320B3BC70 TE28F320B3TC90 TE28F320B3BC90 TE28F320B3TA100 TE28F320B3BA100 TE28F320B3TA110 TE28F320B3BA110 JS28F320B3TD70 JS28F320B3BD70
GE28F640B3TC80 GE28F640B3BC80
Ext. Temp. 32 Mbit
GE28F320B3TD70 GE28F320B3BD70 GE28F320B3TC70 GE28F320B3BC70 GE28F320B3TC90 GE28F320B3BC90 PH28F320B3BD70
18 Aug 2005 70
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
Datasheet
www..com
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 34.
Ordering Information: Valid Combinations (Sheet 2 of 2)
40-Lead TSOP 48-Lead TSOP 48-Ball BGA CSP(1,2) 48-Ball VF BGA
Ext. Temp. 16 Mbit
TE28F016B3TA90 TE28F016B3BA90 TE28F016B3TA110 TE28F016B3BA110
TE28F160B3TD70 TE28F160B3BD70 TE28F160B3TC70 TE28F160B3BC70 TE28F160B3TC80 TE28F160B3BC80 TE28F160B3TC90 TE28F160B3BC90 TE28F160B3TA90 TE28F160B3BA90 TE28F160B3TA110 TE28F160B3BA110 JS28F160B3TA70 JS28F160B3BD70
GT28F160B3TA90(3) GT28F160B3BA90(3) GT28F160B3TA110(3) GT28F160B3BA110(3)
GE28F160B3TD70 GE28F160B3BD70 GE28F160B3TC70 GE28F160B3BC70 GE28F160B3TC80 GE28F160B3BC80 GE28F160B3TC90 GE28F160B3BC90 PH28F160B3TD70 PH28F160B3BD70
Ext. Temp. 8 Mbit
TE28F800B3TA90 TE28F800B3BA90 TE28F800B3TA110 TE28F800B3BA110
GE28F800B3TA70 GE28F800B3BA70 GE28F800B3TA90 GE28F800B3BA90
Notes: 1. The 48-ball BGA package top side mark reads F160B3. This mark is identical for both x8 and x16 products. All product shipping boxes or trays provide the correct information regarding bus architecture. However, once the flash memory devices are removed from the shipping media, differentiating based on the top side mark might be difficult. The device identifier (accessible through the Device ID command: see Section 11.2, "Read Identifier" on page 56 for further details) enables x8 and x16 BGA package product differentiation. 2. The second line of the 48-ball BGA package top side mark specifies assembly codes. For samples only, the first character signifies either: - E for engineering samples, or - S for silicon daisy-chain samples. All other assembly codes without an E or an S as the first character are production units. 3. Intel recommends using.18 m Intel Advanced Boot Block Products.
Datasheet
Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020
(R)
18 Aug 2005 71

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